ASP-DAC 2002: Bangalore, India

Proceedings of the ASPDAC 2002 / VLSI Design 2002, CD-ROM, 7-11 January 2002, Bangalore, India. IEEE 2002, ISBN 0-7695-1299-2 BibTeX

@proceedings{DBLP:conf/aspdac/2002,
  title     = {Proceedings of the ASPDAC 2002 / VLSI Design 2002, CD-ROM, 7-11
               January 2002, Bangalore, India},
  booktitle = {ASP-DAC},
  publisher = {IEEE},
  year      = {2002},
  isbn      = {0-7695-1299-2},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

Biswadip Mitra:
Consumer Digitization: Accelerating DSP Applications, Growing VLSI Design Challenges. 3-4
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Kazuo Yano:
LSI Design in the 21st Century: Key Changes in Sub-1V Giga-Integration Era. 5
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Aart J. de Geus:
Electronic Industry on Fire: How to Survive and Thrive. 6
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Martin F. H. Schuurmans:
Digital Watermarking. 7-10
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Subir K. Roy, S. Ramesh, Supratik Chakraborty, Tsuneo Nakata, Sreeranga P. Rajan:
Functional Verification of System on Chips-Practices, Issues and Challenges. 11-13
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Pieter van der Wolf, W. M. Kruijtzer, Jos T. J. van Eijndhoven:
T2: System-Level Design of Embedded Media Systems. 14-15
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Stefan Rusu, Manoj Sachdev, Christer Svensson, B. Nauta:
T3: Trends and Challenges in VLSI Technology Scaling towards 100nm. 16-17
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M. V. Atre, P. S. Subramanian, H. Narayanan:
T4: Mathematical Methods in VLSI. 18-19
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Vishwani D. Agrawal, Michael L. Bushnell:
T5: Electronic Testing for SOC Designers. 20
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Luciano Lavagno, Sujit Dey, Rajesh Gupta:
Specification, Modeling and Design Tools for System-on-Chip. 21-23
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R. Lal, P. R. Apte, K. N. Bhat, G. Bose, S. Chandra, D. K. Sharma:
T7: MEMS: Technology, Design, CAD and Applications. 24-25
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Jordi Cortadella, Alexandre Yakovlev, Jim D. Garside:
T8: Logic Design of Asynchronous Circuits. 26-30
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David Duarte, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mary Jane Irwin:
Evaluating Run-Time Techniques for Leakage Power Reduction. 31-38
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Wenjie Jiang, Vivek Tiwari, Erik de la Iglesia, Amit Sinha:
Topological Analysis for Leakage Prediction of Digital Circuits. 39-44
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Rahul Kumar, C. P. Ravikumar:
Leakage Power Estimation for Deep Submicron Circuits in an ASIC Design Environment. 45-50
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Fei Li, Lei He, Kewal K. Saluja:
Estimation of Maximum Power-up Current. 51-58
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Joong-Ho Kim, Erdem Matoglu, Jinwoo Choi, Madhavan Swaminathan:
Modeling of Multi-Layered Power Distribution Planes Including Via Effects Using Transmission Matrix Method. 59-64
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Seung Hoon Choi, Bipul Chandra Paul, Kaushik Roy:
Dynamic Noise Analysis with Capacitive and Inductive Coupling. 65-70
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Makoto Nagata, Youichi Nishimori, Takashi Morie, Atsushi Iwata, Yoshitaka Murasaka:
Substrate Noise Analysis with Compact Digital Noise Injection and Substrate Models. 71-76
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Kanak Agarwal, Yu Cao, Takashi Sato, Dennis Sylvester, Chenming Hu:
Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis. 77-86
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Rupesh S. Shelar, Sachin S. Sapatnekar:
An Efficient Algorithm for Low Power Pass Transistor Logic Synthesis. 87-92
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Hiroshi Saito, Takashi Nanya, Alex Kondratyev:
Design of Asynchronous Controllers with Delay Insensitive Interface. 93-98
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Debasis Samanta, Ajit Pal, Nishant Sinha:
Synthesis of High Performance Low Power Dynamic CMOS Circuits. 99-104
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Vineet Sahula, C. P. Ravikumar, D. Nagchoudhuri:
Improvement of ASIC Design Processes. 105-112
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Haris Lekatsas, Jörg Henkel:
ETAM++: Extended Transition Activity Measure for Low Power Address Bus Designs. 113-120
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Rung-Bin Lin, Chi-Ming Tsai:
Weight-Based Bus-Invert Coding for Low-Power Applications. 121-125
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Wei-Chung Cheng, Jian-Lin Liang, Massoud Pedram:
Software-Only Bus Encoding Techniques for an Embedded System. 126-131
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Payam Heydari, Massoud Pedram:
Interconnect Energy Dissipation in High-Speed ULSI Circuits. 132-140
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N. S. Nagaraj, Poras T. Balsara, Cyrus D. Cantrell:
Embedded Tutorial: Modeling Parasitic Coupling Effects in Reliability Verification. 141
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P. K. Datta, S. Sanyal, D. Bhattacharya:
Losses in Multilevel Crossover in VLSI Interconnects. 142-146
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Qinwei Xu, Pinaki Mazumder:
Rational ABCD Modeling of High-Speed Interconnects. 147-154
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Kuo-Hsing Cheng, Shun-Wen Cheng:
Prioritized Prime Implicant Patterns Puzzle for Novel Logic Synthesis and Optimization. 155-159
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Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya:
A New Synthesis of Symmetric Functions. 160-165
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Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada:
Logic Synthesis for AND-XOR-OR Type Sense-Amplifying PLA. 166-171
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D. Sarkar:
Register Transfer Operation Analysis during Data Path Verification. 172-180
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Ashok K. Murugavel, N. Ranganathan:
A Real Delay Switching Activity Simulator based on Petri net Modeling. 181-186
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Sanjukta Bhanja, N. Ranganathan:
Switching Activity Estimation of Large Circuits using Multiple Bayesian Networks. 187-192
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Debasis Samanta, Ajit Pal:
Optimal Dual -VT Assignment for Low-Voltage Energy-Constrained CMOS Circuits. 193-198
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Eric F. Weglarz, Kewal K. Saluja, Mikko H. Lipasti:
Minimizing Energy Consumption for High-Performance Processing. 199-206
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A. B. Bhattacharyya, Shrutin Ulman:
PREDICTMOS MOSFET Model and its Application to Submicron CMOS Inverter Delay Analysis. 207-212
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Peter M. Lee, Shinji Ito, Takeaki Hashimoto, Tomomasa Touma, Junji Sato, Goichi Yokomizo:
A Parallel and Accelerated Circuit Simulator with Precise Accuracy. 213-218
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Srinath R. Naidu:
Timing Yield Calculation Using an Impulse-train Approach. 219-224
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H. C. Srinivasaiah, Navakanta Bhat:
Implant Dose Sensitivity of 0.1µm CMOS Inverter Delay. 225-232
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Vishal P. Bhatt, M. Balakrishnan, Anshul Kumar:
Exploring the Number of Register Windows in ASIP Synthesis. 233-238
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Oliver Schliebusch, Andreas Hoffmann, Achim Nohl, Gunnar Braun, Heinrich Meyr:
Architecture Implementation Using the Machine Description Language LISA. 239-244
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Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi:
A Framework for Design Space Exploration of Parameterized VLSI Systems. 245-250
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S. Chakraverty, C. P. Ravikumar, D. Roy Choudhuri:
An Evolutionary Scheme for Cosynthesis of Real-Time Systems. 251-260
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Kanishka Lahiri, Sujit Dey, Debashis Panigrahi, Anand Raghunathan:
Battery-Driven System Design: A New Frontier in Low Power Design. 261-267
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Masanori Muroyama, Akihiko Hyodo, Hiroto Yasuura, Tohru Ishihara:
A Power Minimization Technique for Arithmetic Circuits by Cell Selection. 268-273
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Yunsi Fei, Niraj K. Jha:
Functional Partitioning for Low Power Distributed Systems of Systems-on-a-chip. 274-281
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Tohru Ishihara, Kunihiro Asada:
An Architectural Level Energy Reduction Technique For Deep-Submicron Cache Memories. 282-287
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Victor M. DeLaLuz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Anand Sivasubramaniam, Ibrahim Kolcu:
Compiler-Directed Array Interleaving for Reducing Energy in Multi-Bank Memories. 288-296
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S. Natarajan, A. Marshall:
Embedded Tutorial: Technological Innovations to Advance Scalability and Interconnects in Bulk and SOI. 297-298
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Vipul Singhal, C. B. Keshav, K. G. Surnanth, P. R. Suresh:
Transistor Flaring in Deep Submicron-Design Considerations. 299-304
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Shuzhou Fang, Zeyi Wang, Xianlong Hong:
A 3-D Minimum-Order Boundary Integral Equation Technique to Extract Frequency-Dependant Inductance and Resistance in ULSI. 305-310
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Q. Su, Venkataramanan Balakrishnan, Cheng-Kok Koh:
Efficient Approximate Balanced Truncation of General Large-Scale RLC Systems via Krylov Methods. 311-316
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Maryam Shojaei Baghini, Madhav P. Desai:
Impact of Technology Scaling on Metastability Performance of CMOS Synchronizing Latches. 317-324
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P. Klapproth:
Embedded Tutorial: General Architectural Concepts for IP Core Re-Use. 325
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Srinivasan Dasasathyan, Rajesh Radhakrishnan, Ranga Vemuri:
Framework for Synthesis of Virtual Pipelines. 326-331
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Junyu Peng, Samar Abdi, Daniel Gajski:
Automatic Model Refinement for Fast Architecture Exploration. 332-337
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Francisco Barat, Murali Jayapala, Pieter Op de Beeck, Geert Deconinck, K. U. Leuven:
Software Pipelining for Coarse-Grained Reconfigurable Instruction Set Processors. 338-344
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Li Shang, Niraj K. Jha:
Hardware-Software Co-Synthesis of Low Power Real-Time Distributed Embedded Systems with Dynamically Reconfigurable FPGAs. 345-354
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Takayuki Sugawara, Yoshikazu Miyanaga, Norinobu Yoshida:
A Design of Analog C-Matrix Circuits used for Signal/Data Processing. 355-359
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Debapriya Sahu:
A Completely Integrated Low Jitter CMOS PLL for Analog Front Ends in Systems on Chip Environment. 360-365
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Biranchinath Sahu, Aloke K. Dutta:
Automatic Synthesis of CMOS Operational Amplifiers: A Fuzzy Optimization Approach. 366-371
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Jens Lienig, Goeran Jerke, Thorsten Adler:
Electromigration Avoidance in Analog Circuits: Two Methodologies for Current-Driven Routing. 372-380
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Wei Chen, Massoud Pedram, Premal Buch:
Buffered Routing Tree Construction Under Buffer Placement Blockages. 381-386
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Yuchun Ma, Xianlong Hong, Sheqin Dong, Yici Cai, Chung-Kuan Cheng, Jun Gu:
Stairway Compaction using Corner Block List and Its Applications with Rectilinear Blocks. 387-392
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Chi-Ming Tsai, Kun-Tien Kuo, Chyi-Hui Hong, Rung-Bin Lin:
An Adaptive Interconnect-Length Driven Placer. 393-398
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Stelian Alupoaei, Srinivas Katkoori:
Net Clustering Based Macrocell Placement. 399-406
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Vijay Raghunathan, Mani B. Srivastava, Milos D. Ercegovac, Anand Raghunathan:
High-Level Synthesis with SIMD Units. 407-413
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J. Ramanujam, Sandeep Deshpande, Jinpyo Hong, Mahmut T. Kandemir:
A Heuristic for Clock Selection in High-Level Synthesis. 414-419
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Indradeep Ghosh, Krishna Sekar, Vamsi Boppana:
Design for Verification at the Register Transfer Level. 420-425
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Gabriela Nicolescu, S. Martinez, Lobna Kriaa, Wassim Youssef, Sungjoo Yoo, Benoît Charlot, Ahmed Amine Jerraya:
Application of Multi-domain and Multi-language Cosimulation To an Optical MEM Switch Design. 426-434
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Kavish Seth, S. Srinivasan:
VLSI Implementation of 2-D DWT/IDWT Cores using 9/7-tap filter banks based on the Non-expansive Symmetric Extension Scheme. 435-440
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Hak-soo Yu, Jacob A. Abraham:
An Efficient 3-Bit -Scan Multiplier without Overlapping Bits, and Its 64x64 Bit Implementation. 441-446
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Shobha Singh, Shamsi Azmi, Nutan Aarawal, Penaka Phani, Ansuman Rout:
Architecture and Design of a High Performance SRAM for SoC Design. 447-451
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Jinku Choi, Masao Yanagisawa, Tatsuo Ohtsuki, Nozomu Togawa:
VLSI Architecture for a Flexible Motion Estimation with Parameters. 452-457
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Prabhat Mishra, Ashok Halambi, Peter Grun, Nikil D. Dutt, Alexandru Nicolau, Hiroyuki Tomiyama:
Automatic Modeling and Validation of Pipeline Specifications driven by an Architecture Description Language. 458-466
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Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, Masahiro Kawakita:
Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts. 467-472
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Jingyu Xu, Xianlong Hong, Tong Jing, Yici Cai, Jun Gu:
An Efficient Hierarchical Timing-Driven Steiner Tree Algorithm for Global Routing. 473-478
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Hiroaki Yoshida, Motohiro Sera, Masao Kubo, Masahiro Fujita:
Simultaneous Circuit Transformation and Routing. 479-483
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Chunhong Chen:
Probabilistic Analysis of Rectilinear Steiner Trees. 484-488
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Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh:
Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement. 489-498
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Hailong Cui, Sharad C. Seth, Shashank K. Mehta:
A Novel Method to Improve the Test Efficiency of VLSI Tests. 499-504
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Sandeep Koranne:
On Test Scheduling for Core-Based SOCs. 505-510
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Yu Huang, Sudhakar M. Reddy, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan, Yanping Zhang, Wu-Tung Cheng:
Constraint Driven Pin Mapping for Concurrent SOC Testing. 511-516
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Katarzyna Radecka, Zeljko Zilic:
Identifying Redundant Wire Replacements for Synthesis and Verification. 517-523
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Aarti Gupta, Albert E. Casavant, Pranav Ashar, Akira Mukaiyama, Kazutoshi Wakabayashi, X. G. Liu:
Property-Specific Testbench Generation for Guided Simulation. 524-534
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Murali Mohan, Rohini Krishnan, Anshul Kumar, M. Balakrishnan:
A New Divide and Conquer Method for Achieving High Speed Division in Hardware. 535-540
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Tony Han, Sri Parameswaran:
Swasad: An Asic Design For High Speed Dna Sequence Matching. 541-546
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Martin Palkovic, Miguel Miranda, Kristof Denolf, Peter Vos, Francky Catthoor:
Systematic Address and Control Code Transformations for Performance Optimisation of a MPEG-4 Video Decoder. 547-552
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Debashis Panigrahi, Clark N. Taylor, Sujit Dey:
A Hardware/Software Reconfigurable Architecture for Adaptive Wireless Image Communication. 553-560
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Qinwei Xu, Pinaki Mazumder:
Efficient Macromodeling for On-Chip Interconnects. 561-566
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Silke Salewski, Erich Barke:
An Upper Bound for 3D Slicing Floorplans. 567-572
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Jingcao Hu, Yangdong Deng, Radu Marculescu:
System-Level Point-to-Point Communication Synthesis Using Floorplanning Information. 573-579
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Christoph Albrecht, Andrew B. Kahng, Ion I. Mandoiu, Alexander Zelikovsky:
Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing. 580-591
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Yong Chang Kim, Kewal K. Saluja, Vishwani D. Agrawal:
Multiple Faults: Modeling, Simulation and Test. 592-597
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Subhayu Basu, Debdeep Mukhopadhyay, Dipanwita Roy Chowdhury, Indranil Sengupta, Sudipta Bhawmik:
Reformatting Test Patterns for Testing Embedded Core Based System Using Test Access Mechanism (TAM) Switch. 598-603
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Nadir Z. Basturkmen, Sudhakar M. Reddy, Janusz Rajski:
Improved Algorithms for Constructive Multi-Phase Test Point Insertion for Scan Based BIST. 604-614
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Sornavalli Ramanathan, Rituparna Mandal:
Low Power Solution for Wireless Applications. 615-618
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J. Ramanujam, Satish Krishnamurthy, Jinpyo Hong, Mahmut T. Kandemir:
Address Code and Arithmetic Optimizations for Embedded Systems. 619-624
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Yong-Ha Park, Hoi-Jun Yoo, Jeonghoon Kook:
Embedded DRAM (eDRAM) Power-Energy Estimation for System-on-a-chip (SoC) Applications. 625-630
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N. E. Crosbie, Mahmut T. Kandemir, Ibrahim Kolcu, J. Ramanujam, Alok N. Choudhary:
Strategies for Improving Data Locality in Embedded Applications. 631-638
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Shankar Balachandran, PariVallal Kannan, Dinesh Bhatia:
On Routing Demand and Congestion Estimation for FPGAs. 639-646
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Supratik Chakraborty, Rajeev Murgai:
Layout-driven Timing Optimization by Generalized De Morgan Transform. 647-654
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Rituparna Mandal, Dibyendu Goswami, Arup Dash:
Reducing Library Development Cycle Time through an Optimum Layout Create Flow. 655-660
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Evangeline F. Y. Young, M. L. Ho, Chris C. N. Chu:
A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design. 661-670
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Samir Roy, Biplab K. Sikdar, Monalisa Mukherjee, Debesh K. Das:
Degree-Of-Freedom Analysis for Sequential Machines Targeting BIST Quality and Gate Area. 671-676
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Irith Pomeranz, Sudhakar M. Reddy:
A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits. 677-682
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Makoto Sugihara, Hiroto Yasuura:
Optimization of Test Accesses with a Combined BIST and External Test Scheme. 683-688
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Niloy Ganguly, Biplab K. Sikdar, Parimal Pal Chaudhuri:
Design of An On-Chip Test Pattern Generator Without Prohibited Pattern Set (PPS). 689-696
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Dexin Li, Pai H. Chou, Nader Bagherzadeh:
Mode Selection and Mode-Dependency Modeling for Power-Aware Embedded Systems. 697-704
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Anupam Datta, Sidharth Choudhury, Anupam Basu:
Using Randomized Rounding to Satisfy Timing Constraints of Real-Time Preemptive Tasks. 705-710
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Weidong Wang, Anand Raghunathan, Ganesh Lakshminarayana, Niraj K. Jha:
Input Space Adaptive Embedded Software Synthesis. 711-718
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Jiong Luo, Niraj K. Jha:
Static and Dynamic Variable Voltage Scheduling Algorithms for Real-Time Heterogeneous Distributed Embedded Systems. 719-728
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Malay K. Ganai, Adnan Aziz:
Improved SAT-based Bounded Reachability Analysis. 729-734
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Pallab Dasgupta, Arindam Chakrabarti, P. P. Chakrabarti:
Open Computation Tree Logic for Formal Verification of Modules. 735-740
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Raik Brinkmann, Rolf Drechsler:
RTL-Datapath Verification using Integer Linear Programming. 741-746
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Rajarshi Mukherjee, Yozo Nakayama, Toshiya Mima:
Verification of an Industrial CC-NUMA Server. 747-754
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Sagar S. Sabade, Hank Walker:
Evaluation of Statistical Outlier Rejection Methods for IDDQ Limit Setting. 755-760
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C. P. Ravikumar, Rahul Kumar:
Divide-and-Conquer IDDQ Testing for Core-based System Chips. 761-766
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Yun Shao, Sudhakar M. Reddy, Irith Pomeranz:
Path Delay Fault Test Generation for Standard Scan Designs Using State Tuples. 767-772
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Baidya Nath Ray, Parimal Pal Chaudhuri, Prasanta Kumar Nandi:
Test Solution For OTA Based Analog Circuits. 773-788
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Sanjeev Patel:
Development of ASIC Chip-Set for High-End Network Processing Application-A Case Study. 789-794
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Ranjit Yashwante, Bhalchandra Jahagirdar:
IEEE 1394a_2000 Physical Layer ASIC. 795-800
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T. Datta, C. S. Muralidharan:
Definition, Design and Development of the IXE2424 Network Switch/Router ASIC. 801
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