14. ISCA 1987:
Pittsburgh,
PA,
USA
Zary Segall (Ed.):
Proceedings of the 14th Annual International Symposium on Computer Architecture. Pittsburgh,
PA,
June 1987. IEEE Computer Society Press,
1987
- David R. Ditzel, Hubert R. McLellan:
Branch Folding in the CRISP Microprocessor: Reducing Branch Delay to Zero.
2-9 BibTeX
- John A. DeRosa, Henry M. Levy:
An Evaluation of Branch Architectures.
10-16 BibTeX
- Wen-mei W. Hwu, Yale N. Patt:
Checkpoint Repair for Out-of-order Execution Machines.
18-26 BibTeX
- Gurindar S. Sohi, Sriram Vajapeyam:
Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors.
27-34 BibTeX
- John A. Swensen, Yale N. Patt:
Fast Temporary Storage for Serial and Parallel Execution.
35-43 BibTeX
- Kenneth F. Wong, Mark A. Franklin:
Performance Analysis and Design of a Logic Simulation Machine.
46-55 BibTeX
- Kshitij Doshi, Peter J. Varman:
A Modular Systolic Architecture for Image Convolutions.
56-63 BibTeX
- Satoshi Fujita, Reiji Aibara, Masafumi Yamashita, Tadashi Ae:
A Template Matching Algorithm Using Optically-Connected 3-D VLSI Architecture.
64-70 BibTeX
- Bilha Mendelson, Gabriel M. Silberman:
Mapping Data Flow Programs on a VLSI Array of Processors.
72-80 BibTeX
- Dipak Ghosal, Laxmi N. Bhuyan:
Analytical Modeling and Architectural Modifications of a Dataflow Computer.
81-89 BibTeX
- Masaru Takesue:
A Unified Resource Management and Execution Control Mechanism for Data Flow Machines.
90-97 BibTeX
- Shigeo Abe, Tadaaki Bandoh, S. Yamaguchi, Ken-ichi Kurosawa, Kaori Kiriyama:
High Performance Integrated Prolog Processor IPP.
100-107 BibTeX
- Barry S. Fagin, Alvin M. Despain:
Performance Studies of a Parallel Prolog Architecture.
108-116 BibTeX
- Pierluigi Civera, F. Maddaleno, Gianluca Piccinini, Maurizio Zamboni:
An Experimental VLSI Prolog Interpreter: Preliminary Measurements and Results.
117-126 BibTeX
- Olivier Ridoux:
Deterministic and Stochastic Modeling of Parallel Garbage Collection -- Towards Real-Time Criteria.
128-136 BibTeX
- Chengzheng Sun, Tzu Yungui:
The Sharing of Environment in AND-OR-Parallel Execution of Logic Programs.
137-144 BibTeX
- Aloke Guha, Raja Ramnarayan, Matthew Derstine:
Architectural Issues in Designing Symbolic Processors in Optics.
145-151 BibTeX
- Anujan Varma, C. S. Raghavendra:
Rearrangeability of Multistage Shuffle/Exchange Networks.
154-162 BibTeX
- Ramón Beivide, Enrique Herrada, José L. Balcázar, Jesús Labarta:
Optimized Mesh-Connected Networks for SIMD and MIMD Architectures.
163-170 BibTeX
- David T. Harper III, J. Robert Jump:
Performance Evaluation of Reduced Bandwidth Multistage Interconnection Networks.
171-175 BibTeX
- Umakishore Ramachandran, Marvin H. Solomon, Mary K. Vernon:
Hardware Support for Interprocess Communication.
178-188 BibTeX
- William J. Dally, Linda Chao, Andrew A. Chien, Soha Hassoun, Waldemar Horwat, Jon Kaplan, Paul Song, Brian Totty, D. Scott Wills:
Architecture of a Message-Driven Processor.
189-196 BibTeX
- Manoj Kumar:
Effect of Storage Allocation/Reclamation Methods on Parallelism and Storage Requirements.
197-205 BibTeX
- J. H. Chang, H. Chao, Kimming So:
Cache Design of a Sub-Micron CMOS System/370.
208-213 BibTeX
- Martin Freeman:
An Architectural Perspective on a Memory Access Controller.
214-223 BibTeX
- Kifung C. Cheung, Gurindar S. Sohi, Kewal K. Saluja, Dhiraj K. Pradhan:
Organization and Analysis of a Gracefully-Degrading Interleaved Memory System.
224-231 BibTeX
- Christoph Scheurich, Michel Dubois:
Correct Memory Operation of Cache-Based Multiprocessors.
234-243 BibTeX
- Andrew W. Wilson Jr.:
Hierarchical Cache/Bus Architecture for Shared Memory Multiprocessors.
244-252 BibTeX
- Roland L. Lee, Pen-Chung Yew, Duncan H. Lawrie:
Multiprocessor Cache Design Considerations.
253-262 BibTeX
- Richard J. Eickemeyer, Janak H. Patel:
Performance Evaluation of Multiple Register Sets.
264-271 BibTeX
- Timothy J. Stanley, Robert G. Wedig:
A Performance Analysis of Automatically Managed Top of Stack Buffers.
272-281 BibTeX
- Brian B. Moore, Andris Padegs, Ronald M. Smith, Werner Buchholz:
Concepts of the System/370 Vector Architecture.
282-288 BibTeX
- Andrew R. Pleszkun, James R. Goodman, Wei-Chung Hsu, R. T. Joersz, George E. Bier, Philip J. Woest, P. B. Schechter:
WISQ: A Restartable Architecture Using Queues.
290-299 BibTeX
- Paul Chow, Mark Horowitz:
Architectural Tradeoffs in the Design of MIPS-X.
300-308 BibTeX
- David R. Ditzel, Hubert R. McLellan, Alan D. Berenbaum:
The Hardware Architecture of the CRISP Microprocessor.
309-319 BibTeX
Copyright © Wed Aug 20 20:05:36 2008
by Michael Ley (ley@uni-trier.de)
