Venkatesh Akella

2008
25	EE	John Oliver, Rajeevan Amirtharajah, Venkatesh Akella, Frederic T. Chong: Credit-based dynamic reliability management using online wearout detection. Conf. Computing Frontiers 2008: 139-148
24	EE	Amit Hadke, Tony Benavides, S. J. Ben Yoo, Rajeevan Amirtharajah, Venkatesh Akella: OCDIMM: Scaling the DRAM Memory Wall Using WDM Based Optical Interconnects. Hot Interconnects 2008: 57-63
2007
23	EE	John Y. Oliver, Rajeevan Amirtharajah, Venkatesh Akella, Roland Geyer, Frederic T. Chong: Life Cycle Aware Computing: Reusing Silicon Technology. IEEE Computer 40(12): 56-61 (2007)
2006
22	EE	John Oliver, Ravishankar Rao, Michael Brown, Jennifer Mankin, Diana Franklin, Frederic T. Chong, Venkatesh Akella: Tile size selection for low-power tile-based architectures. Conf. Computing Frontiers 2006: 83-94
21	EE	Ravishankar Rao, Justin Wenck, Diana Franklin, Rajeevan Amirtharajah, Venkatesh Akella: Segmented Bitline Cache: Exploiting Non-uniform Memory Access Patterns. HiPC 2006: 123-134
2005
20	EE	Venkatesh Akella, Mihaela van der Schaar, Wen-Fu Kao: Proactive Energy Optimization Algorithms for Wavelet-Based Video Codecs on Power-Aware Processors. ICME 2005: 566-569
2004
19		Mihaela van der Schaar, Deepak S. Turaga, Venkatesh Akella: Rate-distortion-complexity adaptive video compression and streaming. ICIP 2004: 2051-2054
18	EE	John Oliver, Ravishankar Rao, Paul Sultana, Jedidiah R. Crandall, Erik Czernikowski, Leslie W. Jones IV, Diana Franklin, Venkatesh Akella, Frederic T. Chong: Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor. ISCA 2004: 150-161
17	EE	John Oliver, Venkatesh Akella, Frederic T. Chong: Efficient orchestration of sub-word parallelism in media processors. SPAA 2004: 225-234
2003
16	EE	John Oliver, Venkatesh Akella: Improving DSP Performance with a Small Amount of Field Programmable Logic. FPL 2003: 520-532
15	EE	John Oliver, Ravishankar Rao, Paul Sultana, Jedidiah R. Crandall, Erik Czernikowski, Leslie W. Jones IV, Dean Copsey, Diana Keen, Venkatesh Akella, Frederic T. Chong: Synchroscalar: Initial Lessons in Power-Aware Design of a Tile-Based Embedded Architecture. PACS 2003: 73-85
2001
14	EE	Tony Werner, Venkatesh Akella: An Asynchronous Superscalar Architecture for Exploiting Instruction-Level Parallelism. ASYNC 2001: 140-151
1999
13	EE	Nithya Raghavan, Venkatesh Akella, Smita Bakshi: Automatic Insertion of Gated Clocks at Register Transfer Level. VLSI Design 1999: 48-54
1998
12		Venkatesh Akella, Nitin H. Vaidya, G. Robert Redinbo: Asynchronous Comparison-Based Decoders for Delay-Insensitive Codes. IEEE Trans. Computers 47(7): 802-811 (1998)
11	EE	Dave Johnson, Venkatesh Akella, Bret Stott: Micropipelined asynchronous discrete cosine transform (DCT/IDCT) processor. IEEE Trans. VLSI Syst. 6(4): 731-740 (1998)
1997
10		Tony Werner, Venkatesh Akella: Asynchronous Processor Survey. IEEE Computer 30(11): 67-76 (1997)
1996
9		Venkatesh Akella, Nitin H. Vaidya, G. Robert Redinbo: Limitations of VLSI Implementation of Delay-Insensitive Codes. FTCS 1996: 208-217
1995
8	EE	Bret Stott, Dave Johnson, Venkatesh Akella: Asynchronous 2-D discrete cosine transform core processor. ICCD 1995: 380-385
1994
7		Prabhakar Kudva, Ganesh Gopalakrishnan, Erik Brunvand, Venkatesh Akella: Performance Analysis and Optimization of Asynchronous Circuits. ICCD 1994: 221-224
6	EE	Venkatesh Akella, Ganesh Gopalakrishnan: Specification and Validation of Control-Intensive IC's in hopCP. IEEE Trans. Software Eng. 20(6): 405-423 (1994)
5		Venkatesh Akella, Ganesh Gopalakrishnan: CFSIM: A Concurrent Compiled Code Functional Simulator for hopCP. Int. Journal in Computer Simulation 4(4): 0- (1994)
4	EE	Ganesh Gopalakrishnan, Venkatesh Akella: High-level optimizations in compiling process descriptions to asynchronous circuits. VLSI Signal Processing 7(1-2): 33-45 (1994)
1993
3		Ganesh Gopalakrishnan, Venkatesh Akella: A transformational approach to asynchronous high-level synthesis. VLSI 1993: 201-210
1992
2	EE	Venkatesh Akella, Ganesh Gopalakrishnan: SHILPA: a high-level synthesis system for self-timed circuits. ICCAD 1992: 587-591
1989
1		Ganesh Gopalakrishnan, Narayana Mani, Venkatesh Akella: Parallel Composition of Lockstep Synchronous Processes for Hardware Validation: Divide-and-Conquer Composition. Automatic Verification Methods for Finite State Systems 1989: 374-382

Coauthor Index

1	Rajeevan Amirtharajah	[21] [23] [24] [25]
2	Smita Bakshi	[13]
3	Tony Benavides	[24]
4	Michael Brown	[22]
5	Erik Brunvand	[7]
6	Frederic T. Chong	[15] [17] [18] [22] [23] [25]
7	Dean Copsey	[15]
8	Jedidiah R. Crandall	[15] [18]
9	Erik Czernikowski	[15] [18]
10	Diana Franklin (Diana Keen)	[15] [18] [21] [22]
11	Roland Geyer	[23]
12	Ganesh Gopalakrishnan	[1] [2] [3] [4] [5] [6] [7]
13	Amit Hadke	[24]
14	Dave Johnson	[8] [11]
15	Leslie W. Jones IV	[15] [18]
16	Wen-Fu Kao	[20]
17	Prabhakar Kudva	[7]
18	Narayana Mani	[1]
19	Jennifer Mankin	[22]
20	John Oliver	[15] [16] [17] [18] [22] [25]
21	John Y. Oliver	[23]
22	Nithya Raghavan	[13]
23	Ravishankar Rao	[15] [18] [21] [22]
24	G. Robert Redinbo	[9] [12]
25	Mihaela van der Schaar	[19] [20]
26	Bret Stott	[8] [11]
27	Paul Sultana	[15] [18]
28	Deepak S. Turaga	[19]
29	Nitin H. Vaidya	[9] [12]
30	Justin Wenck	[21]
31	Tony Werner	[10] [14]
32	S. J. Ben Yoo	[24]

Colors in the list of coauthors