Krste Asanovic

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2008
39EEMark Hampton, Krste Asanovic: Compiling for vector-thread architectures. CGO 2008: 205-215
38EEChristopher Batten, Ajay Joshi, Jason Orcutt, Anatoly Khilo, Benjamin Moss, Charles Holzwarth, Milos Popovic, Hanqing Li, Henry Smith, Judy Hoyt, Franz Kartner, Rajeev Ram, Vladimir Stojanovic, Krste Asanovic: Building Manycore Processor-to-DRAM Networks with Monolithic Silicon Photonics. Hot Interconnects 2008: 21-30
37EERonny Krashinsky, Christopher Batten, Krste Asanovic: Implementing the scale vector-thread processor. ACM Trans. Design Autom. Electr. Syst. 13(3): (2008)
2007
36EEJae W. Lee, Myron King, Krste Asanovic: Continual hashing for efficient fine-grain state inconsistency detection. ICCD 2007: 33-40
35EEJohn Wawrzynek, David Patterson, Mark Oskin, Shih-Lien Lu, Christoforos E. Kozyrakis, James C. Hoe, Derek Chiou, Krste Asanovic: RAMP: Research Accelerator for Multiple Processors. IEEE Micro 27(2): 46-57 (2007)
34EESeongmoo Heo, Ronny Krashinsky, Krste Asanovic: Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy. IEEE Trans. VLSI Syst. 15(9): 1060-1064 (2007)
2006
33EEMark Hampton, Krste Asanovic: Implementing virtual memory in a vector processor with software restart markers. ICS 2006: 135-144
32EEJae W. Lee, Krste Asanovic: METERG: Measurement-Based End-to-End Performance Estimation Technique in QoS-Capable Multiprocessors. IEEE Real Time Technology and Applications Symposium 2006: 135-147
31EEKenneth R. Barr, Krste Asanovic: Energy-aware lossless data compression. ACM Trans. Comput. Syst. 24(3): 250-291 (2006)
30EEC. Scott Ananian, Krste Asanovic, Bradley C. Kuszmaul, Charles E. Leiserson, Sean Lie: Unbounded Transactional Memory. IEEE Micro 26(1): 59-69 (2006)
2005
29EEC. Scott Ananian, Krste Asanovic, Bradley C. Kuszmaul, Charles E. Leiserson, Sean Lie: Unbounded Transactional Memory. HPCA 2005: 316-327
28EEMichael Zhang, Krste Asanovic: Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled Chip Multiprocessors. ISCA 2005: 336-345
27EESeongmoo Heo, Krste Asanovic: Replacing global wires with an on-chip network: a power analysis. ISLPED 2005: 369-374
26EEEmmett Witchel, Junghwan Rhee, Krste Asanovic: Mondrix: memory isolation for linux using mondriaan memory protection. SOSP 2005: 31-44
25EEJessica H. Tseng, Krste Asanovic: A Speculative Control Scheme for an Energy-Efficient Banked Register Fil. IEEE Trans. Computers 54(6): 741-751 (2005)
2004
24EERonny Krashinsky, Christopher Batten, Mark Hampton, Steve Gerding, Brian Pharris, Jared Casper, Krste Asanovic: The Vector-Thread Architecture. ISCA 2004: 52-63
23EESeongmoo Heo, Krste Asanovic: Power-optimal pipelining in deep submicron technology. ISLPED 2004: 218-223
22EEChristopher Batten, Ronny Krashinsky, Steve Gerding, Krste Asanovic: Cache Refill/Access Decoupling for Vector Machines. MICRO 2004: 331-342
21EERonny Krashinsky, Christopher Batten, Mark Hampton, Steve Gerding, Brian Pharris, Jared Casper, Krste Asanovic: The Vector-Thread Architecture. IEEE Micro 24(6): 84-90 (2004)
2003
20 Emmett Witchel, Krste Asanovic: Hardware Works, Software Doesn't: Enforcing Modularity with Mondriaan Memory Protection. HotOS 2003: 139-144
19EEJessica H. Tseng, Krste Asanovic: Banked Multiported Register Files for High-Frequency Superscalar Microprocessors. ISCA 2003: 62-71
18EESeongmoo Heo, Kenneth Barr, Krste Asanovic: Reducing power density through activity migration. ISLPED 2003: 217-222
17EEKenneth Barr, Krste Asanovic: Energy Aware Lossless Data Compression. MobiSys 2003
2002
16EEEmmett Witchel, Josh Cates, Krste Asanovic: Mondrian memory protection. ASPLOS 2002: 304-316
15EESeongmoo Heo, Kenneth Barr, Mark Hampton, Krste Asanovic: Dynamic Fine-Grain Leakage Reduction Using Leakage-Biased Bitlines. ISCA 2002: 137-147
14EEMichael Zhang, Krste Asanovic: Fine-grain CAM-tag cache resizing using miss tags. ISLPED 2002: 130-135
2001
13EESeongmoo Heo, Ronny Krashinsky, Krste Asanovic: Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy. ARVLSI 2001: 59-74
12EEHeidi Pan, Krste Asanovic: Heads and tails: a variable-length instruction format supporting parallel fetch and decode. CASES 2001: 168-175
11EEEmmett Witchel, Samuel Larsen, C. Scott Ananian, Krste Asanovic: Direct addressed caches for reduced power consumption. MICRO 2001: 124-133
10EEMichael Sung, Ronny Krashinsky, Krste Asanovic: Multithreading decoupled architectures for complexity-effective general purpose computing. SIGARCH Computer Architecture News 29(5): 56-61 (2001)
2000
9EELuis Villa, Michael Zhang, Krste Asanovic: Dynamic zero compression for cache energy reduction. MICRO 2000: 214-220
1997
8 David A. Patterson, Krste Asanovic, Aaron B. Brown, Richard Fromm, Jason Golbus, Benjamin Gribstad, Kimberly Keeton, Christoforos E. Kozyrakis, David Martin, Stylianos Perissakis, Randi Thomas, Noah Treuhaft, Katherine A. Yelick: Intelligent RAM (IRAM): The Industrial Setting, Applications and Architectures. ICCD 1997: 2-7
7 Krste Asanovic: A Fast Kohonen Net Implementation for Spert-II. IWANN 1997: 792-800
6EEJeff Bilmes, Krste Asanovic, Chee-Whye Chin, James Demmel: Optimizing Matrix Multiply Using PHiPAC: A Portable, High-Performance, ANSI C Coding Methodology. International Conference on Supercomputing 1997: 340-347
5 Christoforos E. Kozyrakis, Stylianos Perissakis, David A. Patterson, Thomas E. Anderson, Krste Asanovic, Neal Cardwell, Richard Fromm, Jason Golbus, Benjamin Gribstad, Kimberly Keeton, Randi Thomas, Noah Treuhaft, Katherine A. Yelick: Scalable Processors in the Billion-Transistor Era: IRAM. IEEE Computer 30(9): 75-78 (1997)
1996
4 John Wawrzynek, Krste Asanovic, Brian Kingsbury, David Johnson, James Beck, Nelson Morgan: Spert-II: A Vector Microprocessor System. IEEE Computer 29(3): 79-86 (1996)
1995
3EEJohn Wawrzynek, Krste Asanovic, Brian Kingsbury, James Beck, David Johnson, Nelson Morgan: SPERT-II: A Vector Microprocessor System and its Application to Large Problems in Backpropagation Training. NIPS 1995: 619-625
1993
2EEKrste Asanovic, James Beck, Jerry Feldman, Nelson Morgan, John Wawrzynek: Designing A Connectionist Network Supercomputer. Int. J. Neural Syst. 4(4): 317-326 (1993)
1EEKrste Asanovic, Nelson Morgan, John Wawrzynek: Using simulations of reduced precision arithmetic to design a neuro-microprocessor. VLSI Signal Processing 6(1): 33-44 (1993)

Coauthor Index

1C. Scott Ananian [11] [29] [30]
2Thomas E. Anderson [5]
3Kenneth Barr [15] [17] [18]
4Kenneth R. Barr [31]
5Christopher Batten [21] [22] [24] [37] [38]
6James Beck [2] [3] [4]
7Jeff A. Bilmes (Jeff Bilmes) [6]
8Aaron B. Brown [8]
9Neal Cardwell [5]
10Jared Casper [21] [24]
11Josh Cates [16]
12Chee-Whye Chin [6]
13Derek Chiou [35]
14James Demmel [6]
15Jerry Feldman [2]
16Richard Fromm [5] [8]
17Steve Gerding [21] [22] [24]
18Jason Golbus [5] [8]
19Benjamin Gribstad [5] [8]
20Mark Hampton [15] [21] [24] [33] [39]
21Seongmoo Heo [13] [15] [18] [23] [27] [34]
22James C. Hoe [35]
23Charles Holzwarth [38]
24Judy Hoyt [38]
25David Johnson [3] [4]
26Ajay Joshi [38]
27Franz Kartner [38]
28Kimberly Keeton [5] [8]
29Anatoly Khilo [38]
30Myron King [36]
31Brian Kingsbury [3] [4]
32Christoforos E. Kozyrakis (Christos Kozyrakis) [5] [8] [35]
33Ronny Krashinsky [10] [13] [21] [22] [24] [34] [37]
34Bradley C. Kuszmaul [29] [30]
35Samuel Larsen [11]
36Jae W. Lee [32] [36]
37Charles E. Leiserson [29] [30]
38Hanqing Li [38]
39Sean Lie [29] [30]
40Shih-Lien Lu [35]
41David Martin [8]
42Nelson Morgan [1] [2] [3] [4]
43Benjamin Moss [38]
44Jason Orcutt [38]
45Mark Oskin [35]
46Heidi Pan [12]
47David Patterson [35]
48David A. Patterson [5] [8]
49Stylianos Perissakis [5] [8]
50Brian Pharris [21] [24]
51Milos Popovic [38]
52Rajeev Ram [38]
53Junghwan Rhee [26]
54Henry Smith [38]
55Vladimir Stojanovic [38]
56Michael Sung [10]
57Randi Thomas [5] [8]
58Noah Treuhaft [5] [8]
59Jessica H. Tseng [19] [25]
60Luis Villa [9]
61John Wawrzynek [1] [2] [3] [4] [35]
62Emmett Witchel [11] [16] [20] [26]
63Katherine A. Yelick [5] [8]
64Michael Zhang [9] [14] [28]

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Copyright © Fri Oct 3 18:41:27 2008 by Michael Ley (ley@uni-trier.de)