| 2008 |
|---|
| 64 | EE | Wen Ji,
Yuta Abe,
Takeshi Ikenaga,
Satoshi Goto:
A cost-efficient partially-parallel irregular LDPC decoder based on sum-delta message passing algorithm.
ACM Great Lakes Symposium on VLSI 2008: 207-212 |
| 63 | EE | Yibo Fan,
Jidong Wang,
Takeshi Ikenaga,
Yukiyasu Tsunoo,
Satoshi Goto:
An Unequal Secure Encryption Scheme for H.264/AVC Video Compression Standard.
IEICE Transactions 91-A(1): 12-21 (2008) |
| 62 | EE | Zhenxing Chen,
Yang Song,
Takeshi Ikenaga,
Satoshi Goto:
Adaptive Search Range Algorithms for Variable Block Size Motion Estimation in H.264/AVC.
IEICE Transactions 91-A(4): 1015-1022 (2008) |
| 61 | EE | Kazunori Shimizu,
Nozomu Togawa,
Takeshi Ikenaga,
Satoshi Goto:
Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique.
IEICE Transactions 91-A(4): 1054-1061 (2008) |
| 60 | EE | Yibo Fan,
Takeshi Ikenaga,
Satoshi Goto:
A High-Speed Design of Montgomery Multiplier.
IEICE Transactions 91-A(4): 971-977 (2008) |
| 59 | EE | Yiqing Huang,
Zhenyu Liu,
Yang Song,
Satoshi Goto,
Takeshi Ikenaga:
Parallel Improved HDTV720p Targeted Propagate Partial SAD Architecture for Variable Block Size Motion Estimation in H.264/AVC.
IEICE Transactions 91-A(4): 987-997 (2008) |
| 58 | EE | Yibo Fan,
Takeshi Ikenaga,
Satoshi Goto:
Reconfigurable Variable Block Size Motion Estimation Architecture for Search Range Reduction Algorithm.
IEICE Transactions 91-C(4): 440-448 (2008) |
| 57 | EE | Qin Liu,
Seiichiro Hiratsuka,
Kazunori Shimizu,
Shinsuke Ushiki,
Satoshi Goto,
Takeshi Ikenaga:
A 41 mW VGA@30 fps Quadtree Video Encoder for Video Surveillance Systems.
IEICE Transactions 91-C(4): 449-456 (2008) |
| 56 | EE | Lingfeng Li,
Yang Song,
Shen Li,
Takeshi Ikenaga,
Satoshi Goto:
A Hardware Architecture of CABAC Encoding and Decoding with Dynamic Pipeline for H.264/AVC.
Signal Processing Systems 50(1): 81-95 (2008) |
| 2007 |
|---|
| 55 | EE | Zhenyu Liu,
Yiqing Huang,
Yang Song,
Satoshi Goto,
Takeshi Ikenaga:
Hardware-efficient propagate partial sad architecture for variable block size motion estimation in H.264/AVC.
ACM Great Lakes Symposium on VLSI 2007: 160-163 |
| 54 | EE | Shen Li,
Xianghui Wei,
Takeshi Ikenaga,
Satoshi Goto:
A VLSI architecture design of an edge based fast intra prediction mode decision algorithm for H.264/avc.
ACM Great Lakes Symposium on VLSI 2007: 20-24 |
| 53 | EE | Daiki Nobayashi,
Yutaka Nakamura,
Takeshi Ikenaga,
Yoshiaki Hori:
Development of Single Sign-On System with Hardware Token and Key Management Server.
ICSNC 2007: 73 |
| 52 | EE | Yang Song,
Zhenyu Liu,
Takeshi Ikenaga,
Satoshi Goto:
Enhanced Strict Multilevel Successive Elimination Algorithm for Fast Motion Estimation.
ISCAS 2007: 3659-3662 |
| 51 | EE | Kazunori Shimizu,
Nozomu Togawa,
Takeshi Ikenaga,
Satoshi Goto:
Power-efficient LDPC code decoder architecture.
ISLPED 2007: 359-362 |
| 50 | EE | Yibo Fan,
Jidong Wang,
Takeshi Ikenaga,
Yukiyasu Tsunoo,
Satoshi Goto:
A New Video Encryption Scheme for H.264/AVC.
PCM 2007: 246-255 |
| 49 | EE | Ming Shao,
Zhenyu Liu,
Satoshi Goto,
Takeshi Ikenaga:
Lossless VLSI Oriented Full Computation Reusing Algorithm for H.264/AVC Fractional Motion Estimation.
IEICE Transactions 90-A(4): 756-763 (2007) |
| 48 | EE | Yang Song,
Zhenyu Liu,
Takeshi Ikenaga,
Satoshi Goto:
Lossy Strict Multilevel Successive Elimination Algorithm for Fast Motion Estimation.
IEICE Transactions 90-A(4): 764-770 (2007) |
| 47 | EE | Qi Wang,
Kazunori Shimizu,
Takeshi Ikenaga,
Satoshi Goto:
Efficient Fully-Parallel LDPC Decoder Design with Improved Simplified Min-Sum Algorithms.
IEICE Transactions 90-C(10): 1964-1971 (2007) |
| 46 | EE | Yang Song,
Zhenyu Liu,
Takeshi Ikenaga,
Satoshi Goto:
Low-Power Partial Distortion Sorting Fast Motion Estimation Algorithms and VLSI Implementations.
IEICE Transactions 90-D(1): 108-117 (2007) |
| 45 | EE | Yangxing Liu,
Takeshi Ikenaga,
Satoshi Goto:
Geometrical, Physical and Text/Symbol Analysis Based Approach of Traffic Sign Detection System.
IEICE Transactions 90-D(1): 208-216 (2007) |
| 44 | EE | Shen Li,
Lingfeng Li,
Takeshi Ikenaga,
Shunichi Ishiwata,
Masataka Matsui,
Satoshi Goto:
Content-Based Complexity Reduction Methods for MPEG-2 to H.264 Transcoding.
IEICE Transactions 90-D(1): 90-98 (2007) |
| 43 | EE | Yangxing Liu,
Takeshi Ikenaga,
Satoshi Goto:
An MRF model-based approach to the detection of rectangular shape objects in color images.
Signal Processing 87(11): 2649-2658 (2007) |
| 2006 |
|---|
| 42 | EE | Yang Song,
Takeshi Ikenaga,
Satoshi Goto,
Zhenyu Liu:
Enhanced Partial Distortion Sorting Fast Motion Estimation Algorithm for Low-Power Applications.
APCCAS 2006: 1236-1239 |
| 41 | EE | Kazunori Shimizu,
Nozomu Togawa,
Takeshi Ikenaga,
Satoshi Goto:
Memory-Efficient Accelerating Schedule for LDPC Decoder.
APCCAS 2006: 1317-1320 |
| 40 | EE | Zhen Qiu,
Takeshi Ikenaga,
Satoshi Goto:
Robust Scalable Video Transmission using Object-Oriented Unequal Loss Protection over Internet.
APCCAS 2006: 1583-1586 |
| 39 | EE | Yangxing Liu,
Takeshi Ikenaga,
Satoshi Goto:
A Novel Hybrid Approach of Color Image Segmentation.
APCCAS 2006: 1863-1866 |
| 38 | EE | Jaidong Wang,
Takeshi Ikenaga,
Satoshi Goto,
Kazuo Kunieda,
M. Iwata,
H. Koizumi,
H. Shimazu:
A New Multiscale Line Detection Approach for Aerial Image with Complex Scene.
APCCAS 2006: 1968-1971 |
| 37 | EE | Shen Li,
Lingfeng Li,
Takeshi Ikenaga,
Shunichi Ishiwata,
Masataka Matsui,
Satoshi Goto:
Complexity Based Fast Coding Mode Decision for MPEG-2 / H.264 Video Transcoding.
APCCAS 2006: 574-577 |
| 36 | EE | Lingfeng Li,
Yang Song,
Takeshi Ikenaga,
Satoshi Goto:
A CABAC Encoding Core with Dynamic Pipeline for H.264/AVC Main Profile.
APCCAS 2006: 760-763 |
| 35 | EE | Tatsuyuki Ishikawa,
Kazunori Shimizu,
Takeshi Ikenaga,
Satoshi Goto:
High-throughput decoder for low-density parity-check code.
ASP-DAC 2006: 112-113 |
| 34 | EE | Yangxing Liu,
Takeshi Ikenaga,
Satoshi Goto:
A Novel Approach of Rectangular Shape Object Detection in Color Images Based on An MRF Model.
IEEE ICCI 2006: 386-393 |
| 33 | EE | Jing Wang,
Satoshi Goto,
Kazuo Kunieda,
M. Iwata,
H. Koizumi,
H. Shimazu,
Takeshi Ikenaga:
Geometric Primitives Detection in Aerial Image.
IEEE ICCI 2006: 400-404 |
| 32 | EE | Kazunori Shimizu,
Tatsuyuki Ishikawa,
Nozomu Togawa,
Takeshi Ikenaga,
Satoshi Goto:
A parallel LSI architecture for LDPC decoder improving message-passing schedule.
ISCAS 2006 |
| 31 | EE | Seiichiro Hiratsuka,
Satoshi Goto,
Takeshi Ikenaga:
An ultra-low complexity motion estimation algorithm and its implementation of specific processor.
ISCAS 2006 |
| 30 | EE | Changqi Yang,
Satoshi Goto,
Takeshi Ikenaga:
High performance VLSI architecture of fractional motion estimation in H.264 for HDTV.
ISCAS 2006 |
| 29 | EE | Gang Liu,
Takeshi Ikenaga,
Satoshi Goto,
Takaaki Baba:
A Selective Video Encryption Scheme for MPEG Compression Standard.
IEICE Transactions 89-A(1): 194-202 (2006) |
| 28 | EE | Yang Song,
Zhenyu Liu,
Takeshi Ikenaga,
Satoshi Goto:
A VLSI Architecture for Variable Block Size Motion Estimation in H.264/AVC with Low Cost Memory Organization.
IEICE Transactions 89-A(12): 3594-3601 (2006) |
| 27 | EE | Kazunori Shimizu,
Tatsuyuki Ishikawa,
Nozomu Togawa,
Takeshi Ikenaga,
Satoshi Goto:
Power-Efficient LDPC Decoder Architecture Based on Accelerated Message-Passing Schedule.
IEICE Transactions 89-A(12): 3602-3612 (2006) |
| 26 | EE | Shen Li,
Takeshi Ikenaga,
Hideki Takeda,
Masataka Matsui,
Satoshi Goto:
A Hardware Implementation of a Content-Based Motion Estimation Algorithm for Real-Time MPEG-4 Video Coding.
IEICE Transactions 89-A(4): 932-940 (2006) |
| 25 | EE | Kazunori Shimizu,
Tatsuyuki Ishikawa,
Nozomu Togawa,
Takeshi Ikenaga,
Satoshi Goto:
Partially-Parallel LDPC Decoder Achieving High-Efficiency Message-Passing Schedule.
IEICE Transactions 89-A(4): 969-978 (2006) |
| 24 | EE | Yang Song,
Zhenyu Liu,
Satoshi Goto,
Takeshi Ikenaga:
Scalable VLSI Architecture for Variable Block Size Integer Motion Estimation in H.264/AVC.
IEICE Transactions 89-A(4): 979-988 (2006) |
| 23 | EE | Zhenyu Liu,
Yang Song,
Takeshi Ikenaga,
Satoshi Goto:
A Fine-Grain Scalable and Low Memory Cost Variable Block Size Motion Estimation Architecture for H.264/AVC.
IEICE Transactions 89-C(12): 1928-1936 (2006) |
| 22 | EE | Yangxing Liu,
Satoshi Goto,
Takeshi Ikenaga:
A Contour-Based Robust Algorithm for Text Detection in Color Images.
IEICE Transactions 89-D(3): 1221-1230 (2006) |
| 2005 |
|---|
| 21 | EE | Zhenyu Liu,
Yang Song,
Takeshi Ikenaga,
Satoshi Goto:
A VLSI array processing oriented fast fourier transform algorithm and hardware implementation.
ACM Great Lakes Symposium on VLSI 2005: 291-295 |
| 20 | EE | Kazunori Shimizu,
Nozomu Togawa,
Takeshi Ikenaga,
Satoshi Goto:
Reconfigurable adaptive FEC system with interleaving.
ASP-DAC 2005: 1252-1255 |
| 19 | EE | Lingfeng Li,
Satoshi Goto,
Takeshi Ikenaga:
An efficient deblocking filter architecture with 2-dimensional parallel memory for H.264/AVC.
ASP-DAC 2005: 623-626 |
| 18 | EE | Kazunori Shimizu,
Tatsuyuki Ishikawa,
Takeshi Ikenaga,
Satoshi Goto,
Nozomu Togawa:
Partially-Parallel LDPC Decoder Based on High-Efficiency Message-Passing Algorithm.
ICCD 2005: 503-510 |
| 17 | EE | Yangxing Liu,
Satoshi Goto,
Takeshi Ikenaga:
A Robust Algorithm for Text Detection in Color Images.
ICDAR 2005: 399-405 |
| 16 | EE | Yangxing Liu,
Satoshi Goto,
Takeshi Ikenaga:
An accurate and low complexity approach of detecting circular shape objects in still color images.
ICIP (1) 2005: 333-336 |
| 15 | EE | Seiichiro Hiratsuka,
Satoshi Goto,
Takaaki Baba,
Takeshi Ikenaga:
A locally adaptive subsampling algorithm for software based motion estimation.
ISCAS (3) 2005: 2891-2894 |
| 14 | EE | Hedia Kochkar,
Takeshi Ikenaga,
Kenji Kawahara,
Yuji Oie:
Multi-class QoS routing strategies based on the network state.
Computer Communications 28(11): 1348-1355 (2005) |
| 13 | EE | Zhenyu Liu,
Yang Song,
Takeshi Ikenaga,
Satoshi Goto:
A VLSI Array Processing Oriented Fast Fourier Transform Algorithm and Hardware Implementation.
IEICE Transactions 88-A(12): 3523-3530 (2005) |
| 12 | EE | Kazunori Shimizu,
Nozomu Togawa,
Takeshi Ikenaga,
Satoshi Goto:
Reconfigurable Adaptive FEC System Based on Reed-Solomon Code with Interleaving.
IEICE Transactions 88-D(7): 1526-1537 (2005) |
| 11 | EE | Shen Li,
Yong Jiang,
Takeshi Ikenaga,
Satoshi Goto:
Content-Based Motion Estimation with Extended Temporal-Spatial Analysis.
IEICE Transactions 88-D(7): 1561-1568 (2005) |
| 10 | EE | Lingfeng Li,
Satoshi Goto,
Takeshi Ikenaga:
A Highly Parallel Architecture for Deblocking Filter in H.264/AVC.
IEICE Transactions 88-D(7): 1623-1629 (2005) |
| 2004 |
|---|
| 9 | EE | Yutaka Fukuda,
Hiroyuki Koga,
Takeshi Ikenaga,
Yuji Oie:
Performance evaluation of TCP under dynamic allocation scheme for down-link transmission rate in W-CDMA systems.
Wireless Communications and Mobile Computing 4(2): 223-232 (2004) |
| 2003 |
|---|
| 8 | EE | Takeshi Ikenaga,
Kenji Kawahara,
Tetsuya Takine,
Yuji Oie:
Analysis of Delayed Reservation Scheme in Server-Based QoS Management Network.
AINA 2003: 140-145 |
| 7 | EE | Hiroyuki Koga,
Takeshi Ikenaga,
Yoshiaki Hori,
Yuji Oie:
Out-of-Sequence in Packet Arrivals due to Layer 2 ARQ and Its Impact on TCP Performance in W-CDMA Networks.
SAINT 2003: 398-401 |
| 2002 |
|---|
| 6 | EE | Yoshiaki Ohta,
Kenji Kawahara,
Takeshi Ikenaga,
Yuji Oie:
Performance Evaluation of Channel Switching Scheme for Packet Data Transmission in Radio Network Controller.
NETWORKING 2002: 648-659 |
| 2001 |
|---|
| 5 | EE | Manzoor Hashmani,
Mikio Yoshida,
Takeshi Ikenaga,
Yuji Oie:
Management and Realization of SLA for Providing Network QoS.
ICN (1) 2001: 398-408 |
| 2000 |
|---|
| 4 | EE | Takeshi Ikenaga,
Takeshi Ogura:
Real-time morphology processing using highly parallel 2-D cellular automata CAM2.
IEEE Transactions on Image Processing 9(12): 2018-2026 (2000) |
| 1998 |
|---|
| 3 | | Takeshi Ikenaga,
Takeshi Ogura:
CAM2: A Highly-Parallel Two-Dimensional Cellular Architecture.
IEEE Trans. Computers 47(7): 788-801 (1998) |
| 1997 |
|---|
| 2 | EE | Takeshi Ikenaga,
Takeshi Ogura:
Real-Time Morphology Processing Using Highly Parallel 2D Cellular Automata CAM2.
ICIP (2) 1997: 562-565 |
| 1996 |
|---|
| 1 | | Takeshi Ikenaga,
Takeshi Ogura:
CAM²: A Highly-Parallel 2D Cellular Automata Architecture for Real-Time and Palm-Top Pixel-Level Image Processing.
Euro-Par, Vol. II 1996: 203-212 |
