Abhijit Jas

2008
17	EE	Debasish Das, Kip Killpack, Chandramouli V. Kashyap, Abhijit Jas, Hai Zhou: Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering. ASP-DAC 2008: 486-491
16	EE	Ramtilak Vemu, Abhijit Jas, Jacob A. Abraham, Srinivas Patil, Rajesh Galivanche: A low-cost concurrent error detection technique for processor control logic. DATE 2008: 897-902
15	EE	Avijit Dutta, Abhijit Jas: Combinational Logic Circuit Protection Using Customized Error Detecting and Correcting Codes. ISQED 2008: 68-73
2007
14	EE	Abhijit Jas, Srinivas Patil: Analysis of Specified Bit Handling Capability of Combinational Expander Networks. DFT 2007: 252-260
2006
13	EE	Abhijit Jas, Yi-Shing Chang, Sreejit Chakravarty: An Approach to Minimizing Functional Constraints. DFT 2006: 215-226
2004
12	EE	C. V. Krishna, Abhijit Jas, Nur A. Touba: Achieving high encoding efficiency with partial dynamic LFSR reseeding. ACM Trans. Design Autom. Electr. Syst. 9(4): 500-516 (2004)
11	EE	Abhijit Jas, C. V. Krishna, Nur A. Touba: Weighted pseudorandom hybrid BIST. IEEE Trans. VLSI Syst. 12(12): 1277-1283 (2004)
10	EE	Abhijit Jas, Bahram Pouya, Nur A. Touba: Test data compression technique for embedded cores using virtual scan chains. IEEE Trans. VLSI Syst. 12(7): 775-781 (2004)
2003
9	EE	Abhijit Jas, Jayabrata Ghosh-Dastidar, Mom-Eng Ng, Nur A. Touba: An efficient test vector compression scheme using selective Huffman coding. IEEE Trans. on CAD of Integrated Circuits and Systems 22(6): 797-806 (2003)
2001
8		C. V. Krishna, Abhijit Jas, Nur A. Touba: Test vector encoding using partial LFSR reseeding. ITC 2001: 885-893
7	EE	Abhijit Jas, C. V. Krishna, Nur A. Touba: Hybrid BIST Based on Weighted Pseudo-Random Testing: A New Test Resource Partitioning Scheme. VTS 2001: 2-8
2000
6	EE	Abhijit Jas, Bahram Pouya, Nur A. Touba: Virtual Scan Chains: A Means for Reducing Scan Length in Cores. VTS 2000: 73-78
1999
5	EE	Abhijit Jas, Kartik Mohanram, Nur A. Touba: An Embedded Core DFT Scheme to Obtain Highly Compressed Test Sets. Asian Test Symposium 1999: 275-
4	EE	Abhijit Jas, Nur A. Touba: Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip. ICCD 1999: 418-
3	EE	W. Quddus, Abhijit Jas, Nur A. Touba: Configuration self-test in FPGA-based reconfigurable systems. ISCAS (1) 1999: 97-100
2	EE	Abhijit Jas, Jayabrata Ghosh-Dastidar, Nur A. Touba: Scan Vector Compression/Decompression Using Statistical Coding. VTS 1999: 114-120
1998
1	EE	Abhijit Jas, Nur A. Touba: Test vector decompression via cyclical scan chains and its application to testing core-based designs. ITC 1998: 458-464

Coauthor Index

1	Jacob A. Abraham	[16]
2	Sreejit Chakravarty	[13]
3	Yi-Shing Chang	[13]
4	Debasish Das	[17]
5	Avijit Dutta	[15]
6	Rajesh Galivanche	[16]
7	Jayabrata Ghosh-Dastidar	[2] [9]
8	Chandramouli V. Kashyap	[17]
9	Kip Killpack	[17]
10	C. V. Krishna	[7] [8] [11] [12]
11	Kartik Mohanram	[5]
12	Mom-Eng Ng	[9]
13	Srinivas Patil	[14] [16]
14	Bahram Pouya	[6] [10]
15	W. Quddus	[3]
16	Nur A. Touba	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
17	Ramtilak Vemu	[16]
18	Hai Zhou	[17]

Colors in the list of coauthors