| 2008 |
|---|
| 71 | EE | Fei Wang,
Yu Hu,
Huawei Li,
Xiaowei Li:
A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults.
ASP-DAC 2008: 571-576 |
| 70 | EE | Jia Li,
Qiang Xu,
Yu Hu,
Xiaowei Li:
On reducing both shift and capture power for scan-based testing.
ASP-DAC 2008: 653-658 |
| 69 | EE | Xiang Fu,
Huawei Li,
Yu Hu,
Xiaowei Li:
Robust test generation for power supply noise induced path delay faults.
ASP-DAC 2008: 659-662 |
| 68 | EE | Jia Li,
Qiang Xu,
Yu Hu,
Xiaowei Li:
iFill: An Impact-Oriented X-Filling Method for Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing.
DATE 2008: 1184-1189 |
| 67 | EE | Lei Zhang,
Yinhe Han,
Qiang Xu,
Xiaowei Li:
Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology.
DATE 2008: 891-896 |
| 66 | EE | Fei Wang,
Yu Hu,
Xiaowei Li:
Adaptive Diagnostic Pattern Generation for Scan Chains.
DELTA 2008: 129-132 |
| 65 | EE | Jia Li,
Qiang Xu,
Yu Hu,
Xiaowei Li:
Channel Width Utilization Improvement in Testing NoC-Based Systems for Test Time Reduction.
DELTA 2008: 26-31 |
| 64 | EE | Da Wang,
Rui Li,
Yu Hu,
Huawei Li,
Xiaowei Li:
A Case Study on At-Speed Testing for a Gigahertz Microprocessor.
DELTA 2008: 326-331 |
| 63 | EE | Minjin Zhang,
Huawei Li,
Xiaowei Li:
Static Crosstalk Noise Analysis with Transition Map.
DELTA 2008: 462-465 |
| 62 | EE | Hui Liu,
Huawei Li,
Yu Hu,
Xiaowei Li:
A Scan-Based Delay Test Method for Reduction of Overtesting.
DELTA 2008: 521-526 |
| 61 | EE | Ying Zhang,
Huawei Li,
Xiaowei Li,
Yu Hu:
Codeword Selection for Crosstalk Avoidance and Error Correction on Interconnects.
VTS 2008: 377-382 |
| 60 | EE | Minjin Zhang,
Huawei Li,
Xiaowei Li:
Multiple Coupling Effects Oriented Path Delay Test Generation.
VTS 2008: 383-388 |
| 2007 |
|---|
| 59 | EE | Lei Zhang,
Huawei Li,
Xiaowei Li:
A Routing Algorithm for Random Error Tolerance in Network-on-Chip.
HCI (4) 2007: 1210-1219 |
| 58 | EE | Yinhe Han,
Yu Hu,
Xiaowei Li,
Huawei Li,
Anshuman Chandra:
Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit.
IEEE Trans. VLSI Syst. 15(5): 531-540 (2007) |
| 57 | EE | Guangyan Huang,
Xiaowei Li,
Jing He,
Xin Li:
Data Mining via Minimal Spanning Tree Clustering for Prolonging Lifetime of Wireless Sensor Networks.
International Journal of Information Technology and Decision Making 6(2): 235-251 (2007) |
| 56 | EE | Wei Wang,
Yu Hu,
Yinhe Han,
Xiaowei Li,
You-Sheng Zhang:
Leakage Current Optimization Techniques During Test Based on Don't Care Bits Assignment.
J. Comput. Sci. Technol. 22(5): 673-680 (2007) |
| 2006 |
|---|
| 55 | EE | Hongyang Chen,
Deng Ping,
Yongjun Xu,
Xiaowei Li:
A Novel Localization Scheme Based on RSS Data for Wireless Sensor Networks.
APWeb Workshops 2006: 315-320 |
| 54 | EE | Lei Xie,
Yongjun Xu,
Xiaowei Li,
Yuefei Zhu:
A Lightweight Scheme for Trust Relationship Establishment in Ubiquitous Sensor Networks.
CIT 2006: 229 |
| 53 | EE | Dan Hou,
Xia Shen,
Xiaowei Li,
Yue Liu,
Yongtian Wang:
Digital Restoration of Historical Heritage by Reconstruction from Uncalibrated Images.
Edutainment 2006: 1377-1382 |
| 52 | EE | Tong Liu,
Huawei Li,
Xiaowei Li,
Yinhe Han:
Fast Packet Classification using Group Bit Vector.
GLOBECOM 2006 |
| 51 | EE | Jie Don,
Yu Hu,
Yinhe Han,
Xiaowei Li:
An on-chip combinational decompressor for reducing test data volume.
ISCAS 2006 |
| 50 | EE | Guangyan Huang,
Xiaowei Li,
Jing He:
Clustering Versus Evenly Distributing Energy Dissipation in Wireless Sensor Routing for Prolonging Network Lifetime.
International Conference on Computational Science (2) 2006: 1069-1072 |
| 49 | EE | Huawei Li,
Pei-Fu Shen,
Xiaowei Li:
Robust Test Generation for Precise Crosstalk-induced Path Delay Faults.
VTS 2006: 300-305 |
| 48 | EE | Yu Hu,
Yinhe Han,
Xiaowei Li,
Huawei Li,
Xiaoqing Wen:
Compression/Scan Co-design for Reducing Test Data Volume, Scan-in Power Dissipation, and Test Application Time.
IEICE Transactions 89-D(10): 2616-2625 (2006) |
| 47 | EE | Tao Lv,
Jianping Fan,
Xiaowei Li,
Ling-Yi Liu:
Observability Statement Coverage Based on Dynamic Factored Use-Definition Chains for Functional Verification.
J. Electronic Testing 22(3): 273-285 (2006) |
| 46 | EE | Yinhe Han,
Huawei Li,
Xiaowei Li,
Anshuman Chandra:
Response compaction for system-on-a-chip based on advanced convolutional codes.
Science in China Series F: Information Sciences 49(2): 262-272 (2006) |
| 2005 |
|---|
| 45 | EE | Yongjun Xu,
Jinghua Chen,
Zuying Luo,
Xiaowei Li:
Vector extraction for average total power estimation.
ASP-DAC 2005: 1086-1089 |
| 44 | EE | Yinhe Han,
Yu Hu,
Huawei Li,
Xiaowei Li:
Theoretic analysis and enhanced X-tolerance of test response compact based on convolutional code.
ASP-DAC 2005: 53-58 |
| 43 | EE | Shuguang Gong,
Huawei Li,
Yufeng Xu,
Tong Liu,
Xiaowei Li:
Design of an efficient memory subsystem for network processor.
ASP-DAC 2005: 897-900 |
| 42 | EE | Pei-Fu Shen,
Huawei Li,
Yongjun Xu,
Xiaowei Li:
Non-robust Test Generation for Crosstalk-Induced Delay Faults.
Asian Test Symposium 2005: 120-125 |
| 41 | EE | Yinhe Han,
Xiaowei Li,
Shivakumar Swaminathan,
Yu Hu,
Anshuman Chandra:
Scan Data Volume Reduction Using Periodically Alterable MUXs Decompressor.
Asian Test Symposium 2005: 372-377 |
| 40 | EE | Guangmei Zhang,
Chen Rui,
Xiaowei Li,
Han Congying:
The Automatic Generation of Basis Set of Path for Path Testing.
Asian Test Symposium 2005: 46-51 |
| 39 | EE | Guangyan Huang,
Guangmei Zhang,
Xiaowei Li,
Yunzhan Gong:
A State Machine for Detecting C/C++ Memory Faults.
Asian Test Symposium 2005: 82-87 |
| 38 | EE | Xiaowei Li,
Yue Liu,
Yongtian Wang,
Dayuan Yan,
Dongdong Weng,
Tao Yang:
An Improved Colored-Marker Based Registration Method for AR Applications.
ICCSA (3) 2005: 266-273 |
| 37 | EE | Yanzhuo Tan,
Yinhe Han,
Xiaowei Li,
Feiyin Lu,
Yuchuan Chen:
Validation analysis and test flow optimization of VLSI chip.
ISCAS (6) 2005: 5666-5669 |
| 36 | EE | Ji Li,
Yinhe Han,
Xiaowei Li:
Deterministic and low power BIST based on scan slice overlapping.
ISCAS (6) 2005: 5670-5673 |
| 35 | EE | Yinhe Han,
Yu Hu,
Huawei Li,
Xiaowei Li:
Using MUXs Network to Hide Bunches of Scan Chains.
ISQED 2005: 238-243 |
| 34 | EE | Yu Hu,
Xiaowei Li,
Huawei Li,
Xiaoqing Wen:
Compression/Scan Co-Design for Reducing Test Data Volume, Scan-in Power Dissipation and Test Application Time.
PRDC 2005: 175-182 |
| 33 | EE | Yinhe Han,
Yu Hu,
Xiaowei Li,
Huawei Li,
Anshuman Chandra,
Xiaoqing Wen:
Wrapper Scan Chains Design for Rapid and Low Power Testing of Embedded Cores.
IEICE Transactions 88-D(9): 2126-2134 (2005) |
| 32 | EE | Xiaowei Li,
Guanghui Li,
Ming Shao:
Formal Verification Techniques Based on Boolean Satisfiability Problem.
J. Comput. Sci. Technol. 20(1): 38-47 (2005) |
| 31 | EE | Xiaowei Li:
Perface.
J. Comput. Sci. Technol. 20(2): 145-145 (2005) |
| 30 | EE | Yinhe Han,
Xiaowei Li,
Huawei Li,
Anshuman Chandra:
Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction.
J. Comput. Sci. Technol. 20(2): 201-209 (2005) |
| 29 | EE | Huawei Li,
Xiaowei Li:
Selection of Crosstalk-Induced Faults in Enhanced Delay Test.
J. Electronic Testing 21(2): 181-195 (2005) |
| 2004 |
|---|
| 28 | EE | Yu Hu,
Yinhe Han,
Huawei Li,
Tao Lv,
Xiaowei Li:
Pair Balance-Based Test Scheduling for SOCs.
Asian Test Symposium 2004: 236-241 |
| 27 | EE | Guanghui Li,
Xiaowei Li:
Circuit-Width Based Heuristic for Boolean Reasoning.
Asian Test Symposium 2004: 336-341 |
| 26 | EE | Yinhe Han,
Yu Hu,
Huawei Li,
Xiaowei Li,
Anshuman Chandra:
Rapid and Energy-Efficient Testing for Embedded Cores.
Asian Test Symposium 2004: 8-13 |
| 25 | EE | Yinhe Han,
Yu Hu,
Huawei Li,
Xiaowei Li,
Anshuman Chandra:
Response Compaction for Test Time and Test Pins Reduction Based on Advanced Convolutional Codes.
DFT 2004: 298-305 |
| 24 | | Yinhe Han,
Xiaowei Li:
Simultaneous Reduction of Test Data Volume and Testing Power for Scan-Based Test.
ESA/VLSI 2004: 374-381 |
| 23 | | Yongjun Xu,
Zuying Luo,
Xiaowei Li:
A maximum total leakage current estimation method.
ISCAS (2) 2004: 757-760 |
| 22 | | Xiaowei Li:
Conference Reports.
IEEE Design & Test of Computers 21(1): 68- (2004) |
| 21 | EE | Yongjun Xu,
Zuying Luo,
Xiaowei Li,
Li-Jian Li,
Xianlong Hong:
Leakage Current Estimation of CMOS Circuit with Stack Effect.
J. Comput. Sci. Technol. 19(5): 708-717 (2004) |
| 2003 |
|---|
| 20 | EE | Yunzhan Gong,
Wanli Xu,
Xiaowei Li:
An Expression's Single Fault Model and the Testing Methods.
Asian Test Symposium 2003: 110-115 |
| 19 | EE | Tao Lv,
Jianping Fan,
Xiaowei Li:
An Efficient Observability Evaluation Algorithm Based on Factored Use-Def Chains.
Asian Test Symposium 2003: 161-167 |
| 18 | EE | Huawei Li,
Yue Zhang,
Xiaowei Li:
Delay Test Pattern Generation Considering Crosstalk-Induced Effects.
Asian Test Symposium 2003: 178-183 |
| 17 | EE | Yongjun Xu,
Zuying Luo,
Zhiguo Chen,
Xiaowei Li:
Average Leakage Current Macromodeling for Dual-Threshold Voltage Circuits.
Asian Test Symposium 2003: 196-201 |
| 16 | EE | Yinhe Han,
Yongjun Xu,
Huawei Li,
Xiaowei Li,
Anshuman Chandra:
Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Teste.
Asian Test Symposium 2003: 440-445 |
| 15 | EE | Guanghui Li,
Ming Shao,
Xiaowei Li:
Design Error Diagnosis Based on Verification Techniques.
Asian Test Symposium 2003: 474-477 |
| 14 | EE | Ming Shao,
Guanghui Li,
Xiaowei Li:
SAT-Based Algorithm of Verification for Port Order Fault.
Asian Test Symposium 2003: 478-481 |
| 13 | EE | Zhigang Yin,
Yinghua Min,
Xiaowei Li,
Huawei Li:
A Novel RT-Level Behavioral Description Based ATPG Method.
J. Comput. Sci. Technol. 18(3): 308-317 (2003) |
| 2002 |
|---|
| 12 | EE | Zuying Luo,
Xiaowei Li,
Huawei Li,
Shiyuan Yang,
Yinghua Min:
Test Power Optimization Techniques for CMOS Circuits.
Asian Test Symposium 2002: 332-337 |
| 2001 |
|---|
| 11 | EE | Zhigang Yin,
Yinghua Min,
Xiaowei Li:
An Approach to RTL Fault Extraction and Test Generation.
Asian Test Symposium 2001: 219-224 |
| 10 | EE | Xiaowei Li,
Huawei Li,
Yinghua Min:
Reducing Power Dissipation during At-Speed Test Application.
DFT 2001: 116- |
| 9 | EE | Xiaowei Li,
Paul Y. S. Cheung:
A Loop-Based Apparatus for At-Speed Self-Testing.
J. Comput. Sci. Technol. 16(3): 278-285 (2001) |
| 2000 |
|---|
| 8 | EE | Xiaowei Li,
Toshimitsu Masuzawa,
Hideo Fujiwara:
Strong self-testability for data paths high-level synthesis.
Asian Test Symposium 2000: 229-234 |
| 7 | EE | Xiaowei Li,
Paul Y. S. Cheung:
High Level Synthesis for Loop-Based BIST.
J. Comput. Sci. Technol. 15(4): 338-345 (2000) |
| 6 | EE | Xiaowei Li,
Paul Y. S. Cheung:
Exploiting Deterministic TPG for Path Delay Testing.
J. Comput. Sci. Technol. 15(5): 472-479 (2000) |
| 1999 |
|---|
| 5 | EE | Xiaowei Li,
Paul Y. S. Cheung:
Data Path Synthesis for BIST with Low Area Overhead.
ASP-DAC 1999: 275-278 |
| 4 | EE | Xiaowei Li,
Paul Y. S. Cheung:
Exploiting Test Resource Optimization in Data Path Synthesis for BIST.
Great Lakes Symposium on VLSI 1999: 342-343 |
| 3 | EE | Xiaowei Li,
Paul Y. S. Cheung:
An approach to behavioral synthesis for loop-based BIST.
ISCAS (6) 1999: 374-377 |
| 1998 |
|---|
| 2 | EE | Xiaowei Li,
Paul Y. S. Cheung:
Exploiting BIST Approach for Two-Pattern Testing.
Asian Test Symposium 1998: 424-429 |
| 1 | EE | Xiaowei Li,
Paul Y. S. Cheung:
High-Level BIST Synthesis for Delay Testing.
DFT 1998: 318- |
