Panagiotis Manolios

2008
37	EE	Panagiotis Manolios, Sudarshan K. Srinivasan: Automatic verification of safety and liveness for pipelined machines using WEB refinement. ACM Trans. Design Autom. Electr. Syst. 13(3): (2008)
2007
36	EE	Panagiotis Manolios, Sudarshan K. Srinivasan, Daron Vroon: BAT: The Bit-Level Analysis Tool. CAV 2007: 303-306
35	EE	Peter C. Dillinger, Panagiotis Manolios, Daron Vroon, J. Strother Moore: ACL2s: "The ACL2 Sedan". ICSE Companion 2007: 59-60
34	EE	Panagiotis Manolios, Daron Vroon, Gayatri Subramanian: Automating component-based system assembly. ISSTA 2007: 61-72
33	EE	Panagiotis Manolios, Daron Vroon: Efficient Circuit to CNF Conversion. SAT 2007: 4-9
32	EE	Panagiotis Manolios, Marc Galceran Oms, Sergi Oliva Valls: Checking Pedigree Consistency with PCS. TACAS 2007: 339-342
31	EE	Peter C. Dillinger, Panagiotis Manolios, Daron Vroon, J. Strother Moore: ACL2s: "The ACL2 Sedan". Electr. Notes Theor. Comput. Sci. 174(2): 3-18 (2007)
2006
30		Panagiotis Manolios, Matthew Wilding: Proceedings of the Sixth International Workshop on the ACL2 Theorem Prover and its Applications, ACL2 2006, Seattle, Washington, USA, August 15-16, 2006 ACM 2006
29	EE	Panagiotis Manolios, Daron Vroon: Termination Analysis with Calling Context Graphs. CAV 2006: 401-414
28	EE	Roma Kane, Panagiotis Manolios, Sudarshan K. Srinivasan: Monolithic verification of deep pipelines with collapsed flushing. DATE 2006: 1234-1239
27	EE	Panagiotis Manolios, Sudarshan K. Srinivasan, Daron Vroon: Automatic memory reductions for RTL model verification. ICCAD 2006: 786-793
26	EE	Panagiotis Manolios, Daron Vroon: Integrating static analysis and general-purpose theorem proving for termination analysis. ICSE 2006: 873-876
25	EE	Panagiotis Manolios, Yimin Zhang: Implementing Survey Propagation on Graphics Processing Units. SAT 2006: 311-324
24	EE	Panagiotis Manolios: Refinement and Theorem Proving. SFM 2006: 176-210
23	EE	William G. J. Halfond, Alessandro Orso, Panagiotis Manolios: Using positive tainting and syntax-aware evaluation to counter SQL injection attacks. SIGSOFT FSE 2006: 175-185
22	EE	Panagiotis Manolios, Sudarshan K. Srinivasan: A Framework for Verifying Bit-Level Pipelined Machines Based on Automated Deduction and Decision Procedures. J. Autom. Reasoning 37(1-2): 93-116 (2006)
2005
21	EE	Panagiotis Manolios, Sudarshan K. Srinivasan: A Parameterized Benchmark Suite of Hard Pipelined-Machine-Verification Problems. CHARME 2005: 363-366
20	EE	Panagiotis Manolios, Sudarshan K. Srinivasan: Refinement Maps for Efficient Verification of Processor Models. DATE 2005: 1304-1309
19		Panagiotis Manolios, Sudarshan K. Srinivasan: Verification of executable pipelined machines with bit-level interfaces. ICCAD 2005: 855-862
18		Panagiotis Manolios, Sudarshan K. Srinivasan: A complete compositional reasoning framework for the efficient verification of pipelined machines. ICCAD 2005: 863-870
17	EE	Panagiotis Manolios, Sudarshan K. Srinivasan: A computationally ef~cient method based on commitment re~nement maps for verifying pipelined machines. MEMOCODE 2005: 188-197
16	EE	Peter C. Dillinger, Panagiotis Manolios: Enhanced Probabilistic Verification with 3Spin and 3Murphi. SPIN 2005: 272-276
15	EE	Panagiotis Manolios, Daron Vroon: Ordinal Arithmetic: Algorithms and Mechanization. J. Autom. Reasoning 34(4): 387-423 (2005)
2004
14	EE	Panagiotis Manolios, Sudarshan K. Srinivasan: Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements. DATE 2004: 168-175
13	EE	Peter C. Dillinger, Panagiotis Manolios: Bloom Filters in Probabilistic Verification. FMCAD 2004: 367-381
12	EE	Panagiotis Manolios, Daron Vroon: Integrating Reasoning About Ordinal Arithmetic into ACL2. FMCAD 2004: 82-97
11	EE	Peter C. Dillinger, Panagiotis Manolios: Fast and Accurate Bitstate Verification for SPIN. SPIN 2004: 57-75
2003
10	EE	Panagiotis Manolios, Daron Vroon: Algorithms for Ordinal Arithmetic. CADE 2003: 243-257
9	EE	Panagiotis Manolios: A Compositional Theory of Refinement for Branching Time. CHARME 2003: 304-318
8	EE	Panagiotis Manolios, Richard J. Trefler: A lattice-theoretic characterization of safety and liveness. PODC 2003: 325-333
7	EE	Panagiotis Manolios: Brief announcement: branching time refinement. PODC 2003: 334
6	EE	Panagiotis Manolios, J. Strother Moore: Partial Functions in ACL2. J. Autom. Reasoning 31(2): 107-127 (2003)
2001
5		Panagiotis Manolios, Richard J. Trefler: Safety and Liveness in Branching Time. LICS 2001: 366-
4	EE	Panagiotis Manolios, J. Strother Moore: On the desirability of mechanizing calculational proofs. Inf. Process. Lett. 77(2-4): 173-179 (2001)
2000
3	EE	Panagiotis Manolios: Correctness of Pipelined Machines. FMCAD 2000: 161-178
1999
2	EE	Panagiotis Manolios, Kedar S. Namjoshi, Robert Summers: Linking Theorem Proving and Model-Checking with Well-Founded Bisimulation. CAV 1999: 369-379
1	EE	Yuan Yu, Panagiotis Manolios, Leslie Lamport: Model Checking TLA+ Specifications. CHARME 1999: 54-66

Coauthor Index

1	Peter C. Dillinger	[11] [13] [16] [31] [35]
2	William G. J. Halfond	[23]
3	Roma Kane	[28]
4	Leslie Lamport	[1]
5	J. Strother Moore	[4] [6] [31] [35]
6	Kedar S. Namjoshi	[2]
7	Marc Galceran Oms	[32]
8	Alessandro Orso	[23]
9	Sudarshan K. Srinivasan	[14] [17] [18] [19] [20] [21] [22] [27] [28] [36] [37]
10	Gayatri Subramanian	[34]
11	Robert Summers	[2]
12	Richard J. Trefler	[5] [8]
13	Sergi Oliva Valls	[32]
14	Daron Vroon	[10] [12] [15] [26] [27] [29] [31] [33] [34] [35] [36]
15	Matthew Wilding	[30]
16	Yuan Yu	[1]
17	Yimin Zhang	[25]

Colors in the list of coauthors