| 2008 |
|---|
| 12 | EE | Philipp V. Panitz,
Markus Olbrich,
Erich Barke,
Markus Bühler,
Jürgen Koehl:
Considering possible opens in non-tree topology wire delay calculation.
ACM Great Lakes Symposium on VLSI 2008: 17-22 |
| 11 | EE | Markus Olbrich,
Erich Barke:
Distribution arithmetic for stochastical analysis.
ASP-DAC 2008: 537-542 |
| 10 | EE | Darius Grabowski,
Markus Olbrich,
Erich Barke:
Analog circuit simulation using range arithmetics.
ASP-DAC 2008: 762-767 |
| 2007 |
|---|
| 9 | EE | Philipp V. Panitz,
Markus Olbrich,
Erich Barke,
Jürgen Koehl:
Robust wiring networks for DfY considering timing constraints.
ACM Great Lakes Symposium on VLSI 2007: 43-48 |
| 8 | EE | Hedi Harizi,
Robert HauBler,
Markus Olbrich,
Erich Barke:
Efficient Modeling Techniques for Dynamic Voltage Drop Analysis.
DAC 2007: 706-711 |
| 7 | EE | M. Zhang,
Markus Olbrich,
D. Seider,
M. Frerichs,
H. Kinzelbach,
Erich Barke:
CMCal: an accurate analytical approach for the analysis of process variations with non-gaussian parameters and nonlinear functions.
DATE 2007: 243-248 |
| 2005 |
|---|
| 6 | EE | Lars A. Schreiner,
Markus Olbrich,
Erich Barke,
Volker Meyer zu Bexten:
Routing of analog busses with parasitic symmetry.
ISPD 2005: 14-19 |
| 2004 |
|---|
| 5 | EE | Markus Olbrich,
Erich Barke:
Placement Using a Localization Probability Model (LPM).
DATE 2004: 1412 |
| 4 | EE | Idris Kaya,
Silke Salewski,
Markus Olbrich,
Erich Barke:
Wirelength Reduction Using 3-D Physical Design.
PATMOS 2004: 453-462 |
| 2003 |
|---|
| 3 | | Andreas Hermann,
Markus Olbrich,
Erich Barke:
Substrate Modeling and Noise Reduction in Mixed-Signal Circuits.
VLSI-SOC 2003: 13-18 |
| 2001 |
|---|
| 2 | EE | Markus Olbrich,
Achim Rein,
Erich Barke:
An improved hierarchical classification algorithm for structural analysis of integrated circuits.
DATE 2001: 807 |
| 1998 |
|---|
| 1 | EE | Jörn Stohmann,
Klaus Harbich,
Markus Olbrich,
Erich Barke:
An Optimized Design Flow for Fast FPGA-Based Rapid Prototyping.
FPL 1998: 79-88 |
