| 2008 | ||
|---|---|---|
| 8 | EE | Peter Rounce, Alberto Ferreira de Souza: Dynamic Instruction Scheduling in a Trace-based Multi-threaded Architecture. International Journal of Parallel Programming 36(2): 184-205 (2008) |
| 2006 | ||
| 7 | EE | Peter Rounce, Alberto Ferreira de Souza: The mDTSVLIW: a Multi-Threaded Trace-based VLIW Architecture. SBAC-PAD 2006: 63-72 |
| 2000 | ||
| 6 | EE | Alberto Ferreira de Souza, Peter Rounce: On the Scheduling Algorithm of the Dynamically Trace Scheduled VLIW Architecture. IPDPS 2000: 565-572 |
| 5 | EE | Alberto Ferreira de Souza, Peter Rounce: Dynamically Scheduling VLIW Instructions. J. Parallel Distrib. Comput. 60(12): 1480-1511 (2000) |
| 1999 | ||
| 4 | Alberto Ferreira de Souza, Peter Rounce: Effect of Multicycle Intructions on the Integer Performance of the Dynamixcally Trace Scheduled VLIW Architecture. HPCN Europe 1999: 1203-1206 | |
| 3 | EE | Alberto Ferreira de Souza, Peter Rounce: Dynamically Scheduling the Trace Produced During Program Execution into VLIW Instructions. IPPS/SPDP 1999: 248-257 |
| 1998 | ||
| 2 | Alberto Ferreira de Souza, Peter Rounce: Dynamically Trace Scheduled VLIW Architectures. HPCN Europe 1998: 993-995 | |
| 1993 | ||
| 1 | Richard P. Palmer, Peter Rounce: An Architecture for Implementing Control and Signal Processing Neural Networks. IWANN 1993: 702-707 | |
| 1 | Richard P. Palmer | [1] |
| 2 | Alberto Ferreira de Souza | [2] [3] [4] [5] [6] [7] [8] |