Bruno Rouzeyre

2008
28	EE	M. Doulcier, Marie-Lise Flottes, Bruno Rouzeyre: AES-Based BIST: Self-Test, Test Pattern Generation and Signature Analysis. DELTA 2008: 314-321
27	EE	Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre: An Integrated Validation Environment for Differential Power Analysis. DELTA 2008: 527-532
2007
26		Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre: A Novel Parity Bit Scheme for SBox in AES Circuits. DDECS 2007: 267-271
25	EE	Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre: An On-Line Fault Detection Scheme for SBoxes in Secure Circuits. IOLTS 2007: 57-62
24		Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre: A Dependable Parallel Architecture for SBoxes. ReCoSoC 2007: 132-137
23	EE	Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre: Test data compression and TAM design. VLSI-SoC 2007: 178-183
22	EE	Mathieu Scholivé, Vincent Beroulle, Chantal Robach, Marie-Lise Flottes, Bruno Rouzeyre: Mutation Sampling Technique for the Generation of Structural Test Data CoRR abs/0710.4802: (2007)
21	EE	David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre: Securing Scan Control in Crypto Chips. J. Electronic Testing 23(5): 457-464 (2007)
2006
20	EE	David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre: A secure scan design methodology. DATE 2006: 1177-1178
19	EE	Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre: Fitting ATE Channels with Scan Chains: a Comparison between a Test Data Compression Technique and Serial Loading of Scan Chains. DELTA 2006: 295-300
18	EE	David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre: Secure Scan Techniques: A Comparison. IOLTS 2006: 119-124
2005
17	EE	Mathieu Scholivé, Vincent Beroulle, Chantal Robach, Marie-Lise Flottes, Bruno Rouzeyre: Mutation Sampling Technique for the Generation of Structural Test Data. DATE 2005: 1022-1023
2004
16	EE	Marie-Lise Flottes, Regis Poirier, Bruno Rouzeyre: An Arithmetic Structure for Test Data Horizontal Compression. DATE 2004: 428-435
15	EE	Marie-Lise Flottes, Regis Poirier, Bruno Rouzeyre: On Using Test Vector Differences for Reducing Test Pin Numbers. DELTA 2004: 275-280
14	EE	David Hély, Marie-Lise Flottes, Frédéric Bancel, Bruno Rouzeyre, Nicolas Bérard, Michel Renovell: Scan Design and Secure Chip. IOLTS 2004: 219-226
13		Solaiman Rahim, Bruno Rouzeyre, Lionel Torres: A Flip-Flop Matching Engine to Verify Sequential Optimizations. Computers and Artificial Intelligence 23(5): (2004)
2002
12		Michel Robert, Bruno Rouzeyre, Christian Piguet, Marie-Lise Flottes: SOC Design Methodologies, IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on/Chip (VLSI-SOC'01), December 3-5, 2001, Montpellier, France Kluwer 2002
11	EE	Marie-Lise Flottes, Julien Pouget, Bruno Rouzeyre: A Heuristic for Test Scheduling at System Level. DATE 2002: 1124
10	EE	Maciej J. Ciesielski, Priyank Kalla, Zhihong Zeng, Bruno Rouzeyre: Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification. DATE 2002: 285-291
2001
9		Zhihong Zeng, Maciej J. Ciesielski, Bruno Rouzeyre: Functional Test Generation using Constraint Logic Programming. VLSI-SOC 2001: 375-387
8		Marie-Lise Flottes, Julien Pouget, Bruno Rouzeyre: Power-Constrained Test Scheduling for SoCs Under a "no session" Scheme. VLSI-SOC 2001: 401-412
2000
7		David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre: BISTing data paths at behavioral level. ITC 2000: 672-680
1998
6	EE	Marie-Lise Flottes, R. Pires, Bruno Rouzeyre: Alleviating DFT Cost Using Testability Driven HLS. Asian Test Symposium 1998: 46-51
5	EE	Marie-Lise Flottes, R. Pires, Bruno Rouzeyre, L. Volpe: Scanning Datapaths: A Fast and Effective Partial Scan Selection Technique. DATE 1998: 921-922
4	EE	Marie-Lise Flottes, R. Pires, Bruno Rouzeyre, L. Volpe: Low Cost Partial Scan Design: A High Level Synthesis Approach. VTS 1998: 332-340
1995
3		Christian Landrault, Marie-Lise Flottes, Bruno Rouzeyre: Is High-Level Test Synthesis Just Design for Test? ITC 1995: 294
1994
2		Bruno Rouzeyre, D. Dupont, G. Sagnes: Component Selection, Scheduling and Control Schemes for High Level Synthesis. EDAC-ETC-EUROASIC 1994: 482-489
1		Marie-Lise Flottes, D. Hammad, Bruno Rouzeyre: Automatic Synthesis of BISTed Data Paths From High Level Specification. EDAC-ETC-EUROASIC 1994: 591-598

Coauthor Index

1	Frédéric Bancel	[14] [18] [20] [21]
2	Nicolas Bérard	[14]
3	Vincent Beroulle	[17] [22]
4	David Berthelot	[7]
5	Maciej J. Ciesielski	[9] [10]
6	Julien Dalmasso	[19] [23]
7	M. Doulcier	[28]
8	D. Dupont	[2]
9	Marie-Lise Flottes	[1] [3] [4] [5] [6] [7] [8] [11] [12] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28]
10	D. Hammad	[1]
11	David Hély	[14] [18] [20] [21]
12	Priyank Kalla	[10]
13	Christian Landrault	[3]
14	Giorgio Di Natale	[24] [25] [26] [27]
15	Christian Piguet	[12]
16	R. Pires	[4] [5] [6]
17	Regis Poirier	[15] [16]
18	Julien Pouget	[8] [11]
19	Solaiman Rahim	[13]
20	Michel Renovell	[14]
21	Chantal Robach	[17] [22]
22	Michel Robert	[12]
23	G. Sagnes	[2]
24	Mathieu Scholivé	[17] [22]
25	Lionel Torres	[13]
26	L. Volpe	[4] [5]
27	Zhihong Zeng	[9] [10]

Colors in the list of coauthors