| 2008 |
|---|
| 339 | EE | Kaushik Roy,
Prabir Bhattacharya:
Improving Features Subset Selection Using Genetic Algorithms for Iris Recognition.
ANNPR 2008: 292-304 |
| 338 | EE | Swaroop Ghosh,
Kaushik Roy:
Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching.
ASP-DAC 2008: 635-640 |
| 337 | EE | Kunhyuk Kang,
Saakshi Gangwal,
Sang Phill Park,
Kaushik Roy:
NBTI induced performance degradation in logic and memory circuits: how effectively can we approach a reliability solution?
ASP-DAC 2008: 726-731 |
| 336 | EE | Jaydeep P. Kulkarni,
Keejong Kim,
Sang Phill Park,
Kaushik Roy:
Process variation tolerant SRAM array for ultra low voltage applications.
DAC 2008: 108-113 |
| 335 | EE | Jing Li,
Charles Augustine,
Sayeef S. Salahuddin,
Kaushik Roy:
Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement.
DAC 2008: 278-283 |
| 334 | EE | Swaroop Ghosh,
Patrick Ndai,
Kaushik Roy:
A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking.
DATE 2008: 366-371 |
| 333 | EE | Dimitris Gizopoulos,
Kaushik Roy,
Patrick Girard,
Nicola Nicolici,
Xiaoqing Wen:
Power-Aware Testing and Test Strategies for Low Power Devices.
DATE 2008 |
| 332 | EE | Dimitris Gizopoulos,
Kaushik Roy,
Subhasish Mitra,
Pia Sanda:
Soft Errors: System Effects, Protection Techniques and Case Studies.
DATE 2008 |
| 331 | EE | Kaushik Roy,
Prabir Bhattacharya:
Optimal Features Subset Selection Using Genetic Algorithms for Iris Recognition.
ICIAR 2008: 894-904 |
| 330 | EE | Mesut Meterelliyoz,
Jaydeep P. Kulkarni,
Kaushik Roy:
Thermal analysis of 8-T SRAM for nano-scaled technologies.
ISLPED 2008: 123-128 |
| 329 | EE | Swarup Bhunia,
Kaushik Roy:
Low power design under parameter variations.
ISLPED 2008: 137-138 |
| 328 | EE | Swaroop Ghosh,
Jung Hwan Choi,
Patrick Ndai,
Kaushik Roy:
O2C: occasional two-cycle operations for dynamic thermal management in high performance in-order microprocessors.
ISLPED 2008: 189-192 |
| 327 | EE | Aditya Bansal,
Jae-Joon Kim,
Keunwoo Kim,
Saibal Mukhopadhyay,
Ching-Te Chuang,
Kaushik Roy:
Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies.
VLSI Design 2008: 125-130 |
| 326 | EE | Niladri Narayan Mojumder,
Saibal Mukhopadhyay,
Jae-Joon Kim,
Ching-Te Chuang,
Kaushik Roy:
Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry.
VTS 2008: 101-106 |
| 325 | EE | Patrick Ndai,
Swarup Bhunia,
Amit Agarwal,
Kaushik Roy:
Within-Die Variation-Aware Scheduling in Superscalar Processors for Improved Throughput.
IEEE Trans. Computers 57(7): 940-951 (2008) |
| 324 | EE | Saibal Mukhopadhyay,
Hamid Mahmoodi,
Kaushik Roy:
Reduction of Parametric Failures in Sub-100-nm SRAM Array Using Body Bias.
IEEE Trans. on CAD of Integrated Circuits and Systems 27(1): 174-183 (2008) |
| 323 | EE | Jing Li,
Aditya Bansal,
Swaroop Ghosh,
Kaushik Roy:
An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs.
JETC 4(3): (2008) |
| 322 | EE | Jongsun Park,
Kaushik Roy:
A Low Complexity Reconfigurable DCT Architecture to Trade off Image Quality for Power Consumption.
Signal Processing Systems 53(3): 399-410 (2008) |
| 2007 |
|---|
| 321 | EE | Jing Li,
Kunhyuk Kang,
Aditya Bansal,
Kaushik Roy:
High Performance and Low Power Electronics on Flexible Substrate.
DAC 2007: 274-275 |
| 320 | EE | Kunhyuk Kang,
Kee-Jong Kim,
Ahmad E. Islam,
Muhammad Ashraful Alam,
Kaushik Roy:
Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement.
DAC 2007: 358-363 |
| 319 | EE | Kunhyuk Kang,
Kee-Jong Kim,
Kaushik Roy:
Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop.
DAC 2007: 934-939 |
| 318 | EE | Swaroop Ghosh,
Swarup Bhunia,
Kaushik Roy:
Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling.
DATE 2007: 1532-1537 |
| 317 | EE | Myeong-Eun Hwang,
Tamer Cakici,
Kaushik Roy:
Interactive presentation: Process tolerant beta-ratio modulation for ultra-dynamic voltage scaling.
DATE 2007: 1550-1555 |
| 316 | EE | Nilanjan Banerjee,
Georgios Karakonstantis,
Kaushik Roy:
Process variation tolerant low power DCT architecture.
DATE 2007: 630-635 |
| 315 | | Saibal Mukhopadhyay,
Qikai Chen,
Kaushik Roy:
Memories in Scaled Technologies: A Review of Process Induced Failures, Test Methodologies, and Fault Tolerance.
DDECS 2007: 69-74 |
| 314 | EE | Kaushik Roy,
Claire Tomlin:
A New Hybrid State Estimator for Systems with Limited Mode Changes.
HSCC 2007: 487-500 |
| 313 | EE | Georgios Karakonstantis,
Nilanjan Banerjee,
Kaushik Roy,
Chaitali Chakrabarti:
Design methodology to trade off power, output quality and error resiliency: application to color interpolation filtering.
ICCAD 2007: 199-204 |
| 312 | EE | Kunhyuk Kang,
Sang Phill Park,
Kaushik Roy,
Muhammad Ashraful Alam:
Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance.
ICCAD 2007: 730-734 |
| 311 | EE | Jung Hwan Choi,
Jayathi Murthy,
Kaushik Roy:
The effect of process variation on device temperature in FinFET circuits.
ICCAD 2007: 747-751 |
| 310 | EE | Kaushik Roy,
Prabir Bhattacharya:
Collarette Area Localization and Asymmetrical Support Vector Machines for Efficient Iris Recognition.
ICIAP 2007: 3-8 |
| 309 | EE | Kaushik Roy,
Prabir Bhattacharya:
Iris Recognition Based on Zigzag Collarette Region and Asymmetrical Support Vector Machines.
ICIAR 2007: 854-865 |
| 308 | EE | Swaroop Ghosh,
Patrick Ndai,
Swarup Bhunia,
Kaushik Roy:
Tolerance to Small Delay Defects by Adaptive Clock Stretching.
IOLTS 2007: 244-252 |
| 307 | EE | Nilanjan Banerjee,
Jung Hwan Choi,
Kaushik Roy:
A process variation aware low power synthesis methodology for fixed-point FIR filters.
ISLPED 2007: 147-152 |
| 306 | EE | Jaydeep P. Kulkarni,
Keejong Kim,
Kaushik Roy:
A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM.
ISLPED 2007: 171-176 |
| 305 | EE | Keejong Kim,
Hamid Mahmoodi,
Kaushik Roy:
A low-power SRAM using bit-line charge-recycling technique.
ISLPED 2007: 177-182 |
| 304 | EE | Myeong-Eun Hwang,
Seong-Ook Jung,
Kaushik Roy:
Slope interconnect effort: gate-interconnect interdependentdelay model for CMOS logic gates.
ISLPED 2007: 387-390 |
| 303 | EE | Debabrata Mohapatra,
Georgios Karakonstantis,
Kaushik Roy:
Low-power process-variation tolerant arithmetic units using input-based elastic clocking.
ISLPED 2007: 74-79 |
| 302 | EE | Tamer Cakici,
Kee-Jong Kim,
Kaushik Roy:
FinFET Based SRAM Design for Low Standby Power Applications.
ISQED 2007: 127-132 |
| 301 | EE | Patrick Ndai,
Shih-Lien Lu,
Dinesh Somasekhar,
Kaushik Roy:
Fine-Grained Redundancy in Adders.
ISQED 2007: 317-321 |
| 300 | EE | Jaydeep P. Kulkarni,
Kaushik Roy:
A High Performance, Scalable Multiplexed Keeper Technique.
ISQED 2007: 545-549 |
| 299 | EE | Qikai Chen,
Arjun Guha,
Kaushik Roy:
An Accurate Analytical SNM Modeling Technique for SRAMs Based on Butterworth Filter Function.
VLSI Design 2007: 615-620 |
| 298 | EE | Swarup Bhunia,
Saibal Mukhopadhyay,
Kaushik Roy:
Process Variations and Process-Tolerant Design.
VLSI Design 2007: 699-704 |
| 297 | EE | Swaroop Ghosh,
Swarup Bhunia,
Kaushik Roy:
Low-Power and testable circuit synthesis using Shannon decomposition.
ACM Trans. Design Autom. Electr. Syst. 12(4): (2007) |
| 296 | EE | Animesh Datta,
Swarup Bhunia,
Saibal Mukhopadhyay,
Nilanjan Banerjee,
Kaushik Roy:
Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies
CoRR abs/0710.4663: (2007) |
| 295 | EE | Saibal Mukhopadhyay,
Swarup Bhunia,
Kaushik Roy:
Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits
CoRR abs/0710.4729: (2007) |
| 294 | EE | Amit Agarwal,
Kunhyuk Kang,
Swarup Bhunia,
James D. Gallagher,
Kaushik Roy:
Device-Aware Yield-Centric Dual-Vt Design Under Parameter Variations in Nanoscale Technologies.
IEEE Trans. VLSI Syst. 15(6): 660-671 (2007) |
| 293 | EE | Kunhyuk Kang,
Haldun Kufluoglu,
Kaushik Roy,
Muhammad Ashraful Alam:
Impact of Negative-Bias Temperature Instability in Nanoscale SRAM Array: Modeling and Analysis.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(10): 1770-1781 (2007) |
| 292 | EE | Swaroop Ghosh,
Swarup Bhunia,
Kaushik Roy:
CRISTA: A New Paradigm for Low-Power, Variation-Tolerant, and Adaptive Circuit Synthesis Using Critical Path Isolation.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 1947-1956 (2007) |
| 291 | EE | Animesh Datta,
Ashish Goel,
R. T. Cakici,
Hamid Mahmoodi,
D. Lekshmanan,
Kaushik Roy:
Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 1957-1966 (2007) |
| 290 | EE | Jung Hwan Choi,
Aditya Bansal,
Mesut Meterelliyoz,
Jayathi Murthy,
Kaushik Roy:
Self-Consistent Approach to Leakage Power and Temperature Estimation to Predict Thermal Runaway in FinFET Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(11): 2059-2068 (2007) |
| 289 | EE | Bipul Chandra Paul,
Kunhyuk Kang,
Haldun Kufluoglu,
Muhammad Ashraful Alam,
Kaushik Roy:
Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 26(4): 743-751 (2007) |
| 288 | EE | Yongtao Wang,
Khurram Muhammad,
Kaushik Roy:
Design of Sigma-Delta Modulators With Arbitrary Transfer Functions.
IEEE Transactions on Signal Processing 55(2): 677-683 (2007) |
| 287 | EE | Hiroaki Suzuki,
Woopyo Jeong,
Kaushik Roy:
Adaptive Supply Voltage for Low-Power Ripple-Carry and Carry-Select Adders.
IEICE Transactions 90-C(4): 865-876 (2007) |
| 286 | EE | Saibal Mukhopadhyay,
Keunwoo Kim,
Jae-Joon Kim,
Shih-Hsien Lo,
Rajiv V. Joshi,
Ching-Te Chuang,
Kaushik Roy:
Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices.
Microelectronics Journal 38(8-9): 931-941 (2007) |
| 2006 |
|---|
| 285 | EE | Hai Li,
Yiran Chen,
Kaushik Roy,
Cheng-Kok Koh:
SAVS: a self-adaptive variable supply-voltage technique for process- tolerant and power-efficient multi-issue superscalar processor design.
ASP-DAC 2006: 158-163 |
| 284 | EE | Aditya Bansal,
Mesut Meterelliyoz,
Siddharth Singh,
Jung Hwan Choi,
Jayathi Murthy,
Kaushik Roy:
Compact thermal models for estimation of temperature-dependent power/performance in FinFET technology.
ASP-DAC 2006: 237-242 |
| 283 | EE | Ashish Goel,
Swarup Bhunia,
Hamid Mahmoodi-Meimand,
Kaushik Roy:
Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability.
ASP-DAC 2006: 665-670 |
| 282 | EE | Animesh Datta,
Swarup Bhunia,
Jung Hwan Choi,
Saibal Mukhopadhyay,
Kaushik Roy:
Speed binning aware design methodology to improve profit under parameter variations.
ASP-DAC 2006: 712-717 |
| 281 | EE | Hari Ananthan,
Kaushik Roy:
A fully physical model for leakage distribution under process variations in Nanoscale double-gate CMOS.
DAC 2006: 413-418 |
| 280 | EE | Mark M. Budnik,
Arijit Raychowdhury,
Aditya Bansal,
Kaushik Roy:
A high density, carbon nanotube capacitor for decoupling applications.
DAC 2006: 935-938 |
| 279 | EE | Swaroop Ghosh,
Saibal Mukhopadhyay,
Kee-Jong Kim,
Kaushik Roy:
Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM.
DAC 2006: 971-976 |
| 278 | EE | Mark M. Budnik,
Kaushik Roy:
Minimizing ohmic loss and supply voltage variation using a novel distributed power supply network.
DATE 2006: 1116-1121 |
| 277 | EE | Jongsun Park,
Jung Hwan Choi,
Kaushik Roy:
Dynamic bit-width adaptation in DCT: image quality versus computation energy trade-off.
DATE 2006: 520-521 |
| 276 | EE | Bipul Chandra Paul,
Kunhyuk Kang,
Haldun Kufluoglu,
Muhammad Ashraful Alam,
Kaushik Roy:
Temporal performance degradation under NBTI: estimation and design for improved reliability of nanoscale circuits.
DATE 2006: 780-785 |
| 275 | EE | Arijit Raychowdhury,
Bipul Chandra Paul,
Swarup Bhunia,
Kaushik Roy:
Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies.
DATE 2006: 856-861 |
| 274 | EE | Nilanjan Banerjee,
Kaushik Roy,
Hamid Mahmoodi-Meimand,
Swarup Bhunia:
Low power synthesis of dynamic logic circuits using fine-grained clock gating.
DATE 2006: 862-867 |
| 273 | EE | Qikai Chen,
Saibal Mukhopadhyay,
Aditya Bansal,
Kaushik Roy:
Circuit-aware device design methodology for nanometer technologies: a case study for low power SRAM design.
DATE 2006: 983-988 |
| 272 | EE | Kaushik Roy,
Prabir Bhattacharya:
Iris Recognition with Support Vector Machines.
ICB 2006: 486-492 |
| 271 | EE | Jung Hwan Choi,
Aditya Bansal,
Mesut Meterelliyoz,
Jayathi Murthy,
Kaushik Roy:
Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits.
ICCAD 2006: 583-586 |
| 270 | EE | Swaroop Ghosh,
Swarup Bhunia,
Kaushik Roy:
A new paradigm for low-power, variation-tolerant circuit synthesis using critical path isolation.
ICCAD 2006: 619-624 |
| 269 | EE | Kunhyuk Kang,
Haldun Kufluoglu,
Muhammad Ashraful Alam,
Kaushik Roy:
Efficient Transistor-Level Sizing Technique under Temporal Performance Degradation due to NBTI.
ICCD 2006 |
| 268 | EE | Swaroop Ghosh,
Swarup Bhunia,
Arijit Raychowdhury,
Kaushik Roy:
Delay Fault Localization in Test-Per-Scan BIST Using Built-In Delay Sensor.
IOLTS 2006: 31-36 |
| 267 | EE | Ik Joon Chang,
Jae-Joon Kim,
Kaushik Roy:
Robust level converter design for sub-threshold logic.
ISLPED 2006: 14-19 |
| 266 | EE | Arijit Raychowdhury,
Xuanyao Fong,
Qikai Chen,
Kaushik Roy:
Analysis of super cut-off transistors for ultralow power digital logic circuits.
ISLPED 2006: 2-7 |
| 265 | EE | Qikai Chen,
Mesut Meterelliyoz,
Kaushik Roy:
A CMOS Thermal Sensor and Its Applications in Temperature Adaptive Design.
ISQED 2006: 243-248 |
| 264 | EE | Mark M. Budnik,
Kaushik Roy:
Minimizing Ohmic Loss in Future Processor IR Events.
ISQED 2006: 650-658 |
| 263 | EE | Kaushik Roy,
Hamid Mahmoodi-Meimand,
Saibal Mukhopadhyay,
Hari Ananthan,
Aditya Bansal,
Tamer Cakici:
Double-Gate SOI Devices for Low-Power and High-Performance Applications.
VLSI Design 2006: 445-452 |
| 262 | EE | Kunhyuk Kang,
Bipul C. Paul,
Kaushik Roy:
Statistical timing analysis using levelized covariance propagation considering systematic and random variations of process parameters.
ACM Trans. Design Autom. Electr. Syst. 11(4): 848-879 (2006) |
| 261 | EE | Kaushik Roy,
T. M. Mak,
Kwang-Ting (Tim) Cheng:
Test Consideration for Nanometer-Scale CMOS Circuits.
IEEE Design & Test of Computers 23(2): 128-136 (2006) |
| 260 | EE | Amit Agarwal,
Saibal Mukhopadhyay,
Arijit Raychowdhury,
Kaushik Roy,
Chris H. Kim:
Leakage Power Analysis and Reduction for Nanoscale Circuits.
IEEE Micro 26(2): 68-80 (2006) |
| 259 | EE | Mark M. Budnik,
Kaushik Roy:
A Power Delivery and Decoupling Network Minimizing Ohmic Loss and Supply Voltage Variation in Silicon Nanoscale Technologies.
IEEE Trans. VLSI Syst. 14(12): 1336-1346 (2006) |
| 258 | EE | Saibal Mukhopadhyay,
Hamid Mahmoodi-Meimand,
Kaushik Roy:
A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET.
IEEE Trans. VLSI Syst. 14(2): 183-192 (2006) |
| 257 | EE | Dongku Kang,
Hunsoo Choo,
Khurram Muhammad,
Kaushik Roy:
Layout-driven architecture synthesis for high-speed digital filters.
IEEE Trans. VLSI Syst. 14(2): 203-207 (2006) |
| 256 | EE | Chris H. Kim,
Kaushik Roy,
Steven Hsu,
Ram Krishnamurthy,
Shekhar Borkar:
A process variation compensating technique with an on-die leakage current sensor for nanometer scale dynamic circuits.
IEEE Trans. VLSI Syst. 14(6): 646-649 (2006) |
| 255 | EE | Nilanjan Banerjee,
Arijit Raychowdhury,
Kaushik Roy,
Swarup Bhunia,
Hamid Mahmoodi:
Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis.
IEEE Trans. VLSI Syst. 14(9): 1034-1039 (2006) |
| 254 | EE | Arijit Raychowdhury,
Kaushik Roy:
Modeling of metallic carbon-nanotube interconnects for circuit simulations and a comparison with Cu interconnects for scaled technologies.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(1): 58-65 (2006) |
| 253 | EE | Saibal Mukhopadhyay,
Keunwoo Kim,
Ching-Te Chuang,
Kaushik Roy:
Modeling and Analysis of Leakage Currents in Double-Gate Technologies.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2052-2061 (2006) |
| 252 | EE | Animesh Datta,
Swarup Bhunia,
Saibal Mukhopadhyay,
Kaushik Roy:
Delay Modeling and Statistical Design of Pipelined Circuit Under Process Variation.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(11): 2427-2436 (2006) |
| 251 | EE | Aditya Bansal,
Bipul Chandra Paul,
Kaushik Roy:
An Analytical Fringe Capacitance Model for Interconnects Using Conformal Mapping.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2765-2774 (2006) |
| 250 | EE | Swaroop Ghosh,
Swarup Bhunia,
Arijit Raychowdhury,
Kaushik Roy:
A Novel Delay Fault Testing Methodology Using Low-Overhead Built-In Delay Sensor.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2934-2943 (2006) |
| 249 | EE | Jongsun Park,
Khurram Muhammad,
Kaushik Roy:
Efficient modeling of 1/falpha/ noise using multirate process.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(7): 1247-1256 (2006) |
| 248 | EE | Saibal Mukhopadhyay,
Swarup Bhunia,
Kaushik Roy:
Modeling and analysis of loading effect on leakage of nanoscaled bulk-CMOS logic circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(8): 1486-1495 (2006) |
| 247 | EE | Kaushik Roy:
Guest Editorial.
Integration 39(2): 63 (2006) |
| 246 | EE | Bipul Chandra Paul,
Amit Agarwal,
Kaushik Roy:
Low-power design techniques for scaled technologies.
Integration 39(2): 64-89 (2006) |
| 245 | EE | Bipul C. Paul,
Kaushik Roy:
Impact of Body Bias on Delay Fault Testing of Sub-100 nm CMOS Circuits.
J. Electronic Testing 22(2): 115-124 (2006) |
| 2005 |
|---|
| 244 | | Kaushik Roy,
Vivek Tiwari:
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005, San Diego, California, USA, August 8-10, 2005
ACM 2005 |
| 243 | EE | Matthew Cooke,
Hamid Mahmoodi-Meimand,
Qikai Chen,
Kaushik Roy:
Energy recovery clocked dynamic logic.
ACM Great Lakes Symposium on VLSI 2005: 468-471 |
| 242 | EE | Animesh Datta,
Swarup Bhunia,
Saibal Mukhopadhyay,
Kaushik Roy:
A Statistical Approach to Area-Constrained Yield Enhancement for Pipelined Circuits under Parameter Variations.
Asian Test Symposium 2005: 170-175 |
| 241 | EE | Saibal Mukhopadhyay,
Arijit Raychowdhury,
Hamid Mahmoodi-Meimand,
Kaushik Roy:
Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM.
Asian Test Symposium 2005: 176-181 |
| 240 | EE | Swaroop Ghosh,
Swarup Bhunia,
Kaushik Roy:
Shannon Expansion Based Supply-Gated Logic for Improved Power and Testability.
Asian Test Symposium 2005: 404-409 |
| 239 | EE | Swarup Bhunia,
Nilanjan Banerjee,
Qikai Chen,
Hamid Mahmoodi-Meimand,
Kaushik Roy:
A novel synthesis approach for active leakage power reduction using dynamic supply gating.
DAC 2005: 479-484 |
| 238 | EE | Swarup Bhunia,
Hamid Mahmoodi-Meimand,
Arijit Raychowdhury,
Kaushik Roy:
A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application.
DATE 2005: 1136-1141 |
| 237 | EE | Saibal Mukhopadhyay,
Swarup Bhunia,
Kaushik Roy:
Modeling and Analysis of Loading Effect in Leakage of Nano-Scaled Bulk-CMOS Logic Circuits.
DATE 2005: 224-229 |
| 236 | EE | Kunhyuk Kang,
Bipul Chandra Paul,
Kaushik Roy:
Statistical Timing Analysis using Levelized Covariance Propagation.
DATE 2005: 764-769 |
| 235 | EE | Animesh Datta,
Swarup Bhunia,
Saibal Mukhopadhyay,
Nilanjan Banerjee,
Kaushik Roy:
Statistical Modeling of Pipeline Delay and Design of Pipeline under Process Variation to Enhance Yield in sub-100nm Technologies.
DATE 2005: 926-931 |
| 234 | | Kaushik Roy,
Hamid Mahmoodi-Meimand,
Saibal Mukhopadhyay,
Hari Ananthan,
Aditya Bansal,
Tamer Cakici:
Double-gate SOI devices for low-power and high-performance applications.
ICCAD 2005: 217-224 |
| 233 | | Amit Agarwal,
Kunhyuk Kang,
Kaushik Roy:
Accurate estimation and modeling of total chip leakage considering inter- & intra-die process variations.
ICCAD 2005: 736-741 |
| 232 | EE | Patrick Ndai,
Amit Agarwal,
Qikai Chen,
Kaushik Roy:
A Soft Error Monitor Using Switching Current Detection.
ICCD 2005: 185-192 |
| 231 | EE | Nilanjan Banerjee,
Arijit Raychowdhury,
Swarup Bhunia,
Hamid Mahmoodi-Meimand,
Kaushik Roy:
Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis.
ICCD 2005: 206-214 |
| 230 | EE | Arijit Raychowdhury,
Saibal Mukhopadhyay,
Kaushik Roy:
A Feasibility Study of Subthreshold SRAM Across Technology Generations.
ICCD 2005: 417-424 |
| 229 | EE | Chris H. Kim,
Steven Hsu,
Ram Krishnamurthy,
Shekhar Borkar,
Kaushik Roy:
Self Calibrating Circuit Design for Variation Tolerant VLSI Systems.
IOLTS 2005: 100-105 |
| 228 | EE | Qikai Chen,
Saibal Mukhopadhyay,
Hamid Mahmoodi,
Kaushik Roy:
Process Variation Tolerant Online Current Monitor for Robust Systems.
IOLTS 2005: 171-176 |
| 227 | EE | Animesh Datta,
Saibal Mukhopadhyay,
Swarup Bhunia,
Kaushik Roy:
Yield Prediction of High Performance Pipelined Circuit with Respect to Delay Failures in Sub-100nm Technology.
IOLTS 2005: 275-280 |
| 226 | EE | Arijit Raychowdhury,
Swaroop Ghosh,
Kaushik Roy:
A Novel On-Chip Delay Measurement Hardware for Efficient Speed-Binning.
IOLTS 2005: 287-292 |
| 225 | EE | Aditya Bansal,
Kaushik Roy:
Asymmetric halo CMOSFET to reduce static power dissipation with improved performance.
ISCAS (1) 2005: 1-4 |
| 224 | EE | Yongtao Wang,
Kaushik Roy:
A novel low-complexity method for parallel multiplierless implementation of digital FIR filters.
ISCAS (3) 2005: 2020-2023 |
| 223 | EE | Yongtao Wang,
Kaushik Roy:
A new reduced-complexity sphere decoder with true lattice-boundary-awareness for multi-antenna systems.
ISCAS (5) 2005: 4963-4966 |
| 222 | EE | Steven Hsu,
Amit Agarwal,
Kaushik Roy,
Ram Krishnamurthy,
Shekhar Y. Borkar:
An 8.3GHz dual supply/threshold optimized 32b integer ALU-register file loop in 90nm CMOS.
ISLPED 2005: 103-106 |
| 221 | EE | Yiran Chen,
Hai Li,
Kaushik Roy,
Cheng-Kok Koh:
Cascaded carry-select adder (C2SA): a new structure for low-power CSA design.
ISLPED 2005: 115-118 |
| 220 | EE | Amit Agarwal,
Kunhyuk Kang,
Swarup Bhunia,
James D. Gallagher,
Kaushik Roy:
Effectiveness of low power dual-Vt designs in nano-scale technologies under process parameter variations.
ISLPED 2005: 14-19 |
| 219 | EE | Saibal Mukhopadhyay,
Keunwoo Kim,
Ching-Te Chuang,
Kaushik Roy:
Modeling and analysis of total leakage currents in nanoscale double gate devices and circuits.
ISLPED 2005: 8-13 |
| 218 | EE | Animesh Datta,
Swarup Bhunia,
Nilanjan Banerjee,
Kaushik Roy:
A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks.
ISQED 2005: 358-363 |
| 217 | EE | Saibal Mukhopadhyay,
Keunwoo Kim,
Jae-Joon Kim,
Shih-Hsien Lo,
Rajiv V. Joshi,
Ching-Te Chuang,
Kaushik Roy:
Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits.
ISQED 2005: 410-415 |
| 216 | EE | Swarup Bhunia,
Hamid Mahmoodi-Meimand,
Debjyoti Ghosh,
Kaushik Roy:
Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning.
ISQED 2005: 453-458 |
| 215 | EE | Dongku Kang,
Yiran Chen,
Kaushik Roy:
Power Supply Noise-Aware Scheduling and Allocation for DSP Synthesis.
ISQED 2005: 48-53 |
| 214 | EE | Saibal Mukhopadhyay,
Hamid Mahmoodi-Meimand,
Kaushik Roy:
Design of High Performance Sense Amplifier Using Independent Gate Control in sub-50nm Double-Gate MOSFET.
ISQED 2005: 490-495 |
| 213 | EE | Kee-Jong Kim,
Chris H. Kim,
Kaushik Roy:
TFT-LCD Application Specific Low Power SRAM Using Charge-Recycling Technique.
ISQED 2005: 59-64 |
| 212 | EE | Qikai Chen,
Hamid Mahmoodi-Meimand,
Swarup Bhunia,
Kaushik Roy:
Modeling and Testing of SRAM for New Failure Mechanisms Due to Process Variations in Nanoscale CMOS.
VTS 2005: 292-297 |
| 211 | EE | Aiqun Cao,
Naran Sirisantana,
Cheng-Kok Koh,
Kaushik Roy:
Synthesis of skewed logic circuits.
ACM Trans. Design Autom. Electr. Syst. 10(2): 205-228 (2005) |
| 210 | EE | Lih-Yih Chiou,
Swarup Bhunia,
Kaushik Roy:
Synthesis of application-specific highly efficient multi-mode cores for embedded systems.
ACM Trans. Embedded Comput. Syst. 4(1): 168-188 (2005) |
| 209 | EE | Swarup Bhunia,
Animesh Datta,
Nilanjan Banerjee,
Kaushik Roy:
GAARP: A Power-Aware GALS Architecture for Real-Time Algorithm-Specific Tasks.
IEEE Trans. Computers 54(6): 752-766 (2005) |
| 208 | EE | Amit Agarwal,
Bipul Chandra Paul,
Hamid Mahmoodi-Meimand,
Animesh Datta,
Kaushik Roy:
A process-tolerant cache architecture for improved yield in nanoscale technologies.
IEEE Trans. VLSI Syst. 13(1): 27-38 (2005) |
| 207 | EE | Yiran Chen,
Kaushik Roy,
Cheng-Kok Koh:
Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessors.
IEEE Trans. VLSI Syst. 13(1): 75-85 (2005) |
| 206 | EE | Arijit Raychowdhury,
Bipul Chandra Paul,
Swarup Bhunia,
Kaushik Roy:
Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation.
IEEE Trans. VLSI Syst. 13(11): 1213-1224 (2005) |
| 205 | EE | Qikai Chen,
Hamid Mahmoodi-Meimand,
Swarup Bhunia,
Kaushik Roy:
Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations.
IEEE Trans. VLSI Syst. 13(11): 1286-1295 (2005) |
| 204 | EE | Chris H. Kim,
Jae-Joon Kim,
Saibal Mukhopadhyay,
Kaushik Roy:
A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations.
IEEE Trans. VLSI Syst. 13(3): 349-357 (2005) |
| 203 | EE | Swarup Bhunia,
Hamid Mahmoodi-Meimand,
Debjyoti Ghosh,
Saibal Mukhopadhyay,
Kaushik Roy:
Low-power scan design using first-level supply gating.
IEEE Trans. VLSI Syst. 13(3): 384-395 (2005) |
| 202 | EE | Swarup Bhunia,
Kaushik Roy:
A novel wavelet transform-based transient current analysis for fault detection and localization.
IEEE Trans. VLSI Syst. 13(4): 503-507 (2005) |
| 201 | EE | Hai Li,
Chen-Yong Cher,
Kaushik Roy,
T. N. Vijaykumar:
Combined circuit and architectural level variable supply-voltage scaling for low power.
IEEE Trans. VLSI Syst. 13(5): 564-576 (2005) |
| 200 | EE | Saibal Mukhopadhyay,
Hamid Mahmoodi-Meimand,
Kaushik Roy:
Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(12): 1859-1880 (2005) |
| 199 | EE | Saibal Mukhopadhyay,
Arijit Raychowdhury,
Kaushik Roy:
Accurate estimation of total leakage in nanometer-scale bulk CMOS circuits based on device geometry and doping profile.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(3): 363-381 (2005) |
| 198 | EE | Swarup Bhunia,
Arijit Raychowdhury,
Kaushik Roy:
Defect Oriented Testing of Analog Circuits Using Wavelet Analysis of Dynamic Supply Current.
J. Electronic Testing 21(2): 147-159 (2005) |
| 197 | EE | Swarup Bhunia,
Arijit Raychowdhury,
Kaushik Roy:
Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current.
J. Electronic Testing 21(3): 243-255 (2005) |
| 2004 |
|---|
| 196 | | Rajiv V. Joshi,
Kiyoung Choi,
Vivek Tiwari,
Kaushik Roy:
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004, Newport Beach, California, USA, August 9-11, 2004
ACM 2004 |
| 195 | EE | Woopyo Jeong,
Bipul Chandra Paul,
Kaushik Roy:
Adaptive supply voltage technique for low swing interconnects.
ASP-DAC 2004: 284-287 |
| 194 | EE | Yiran Chen,
Kaushik Roy,
Cheng-Kok Koh:
Priority assignment optimization for minimization of current surge in high performance power efficient clock-gated microprocessor.
ASP-DAC 2004: 893-898 |
| 193 | | Cheng-Yi Chen,
Soonkeon Kwon,
Kaushik Roy:
Efficient Communication Channel Utilization for Mapping FFT onto Mesh Array.
Communications in Computing 2004: 167-176 |
| 192 | EE | Seung Hoon Choi,
Bipul Chandra Paul,
Kaushik Roy:
Novel sizing algorithm for yield improvement under process variation in nanometer technology.
DAC 2004: 454-459 |
| 191 | EE | Amit Agarwal,
Chris H. Kim,
Saibal Mukhopadhyay,
Kaushik Roy:
Leakage in nano-scale technologies: mechanisms, impact and design considerations.
DAC 2004: 6-11 |
| 190 | EE | Swarup Bhunia,
Arijit Raychowdhury,
Kaushik Roy:
Trim Bit Setting of Analog Filters Using Wavelet-Based Supply Current Analysis.
DATE 2004: 704-705 |
| 189 | EE | Swarup Bhunia,
Hamid Mahmoodi-Meimand,
Arijit Raychowdhury,
Kaushik Roy:
First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique.
DFT 2004: 314-315 |
| 188 | EE | Saibal Mukhopadhyay,
Hamid Mahmoodi-Meimand,
Kaushik Roy:
Statistical design and optimization of SRAM cell for yield enhancement.
ICCAD 2004: 10-13 |
| 187 | EE | Arijit Raychowdhury,
Kaushik Roy:
A circuit model for carbon nanotube interconnects: comparative study with Cu interconnects for scaled technologies.
ICCAD 2004: 237-240 |
| 186 | EE | Dongku Kang,
Hunsoo Choo,
Kaushik Roy:
Floorplan-Aware Low-Complexity Digital Filter Synthesis for Low-Power & High-Speed.
ICCD 2004: 354-357 |
| 185 | EE | Swarup Bhunia,
Hamid Mahmoodi-Meimand,
Saibal Mukhopadhyay,
Debjyoti Ghosh,
Kaushik Roy:
A Novel Low-Power Scan Design Technique Using Supply Gating.
ICCD 2004: 60-65 |
| 184 | EE | Xiaowei Ding,
Kaushik Roy:
A Novel Bitstream Level Joint Channel Error Concealment Scheme for Realtime Video over Wireless Networks.
INFOCOM 2004 |
| 183 | EE | Amit Agarwal,
Bipul Chandra Paul,
Kaushik Roy:
A Novel Fault Tolerant Cache to Improve Yield in Nanometer Technologies.
IOLTS 2004: 149-154 |
| 182 | EE | Debjyoti Ghosh,
Swarup Bhunia,
Kaushik Roy:
A Technique to Reduce Power and Test Application Time in BIST.
IOLTS 2004: 182-183 |
| 181 | | Hamid Mahmoodi-Meimand,
Kaushik Roy:
Dual-edge triggered level converting flip-flops.
ISCAS (2) 2004: 661-664 |
| 180 | | Hamid Mahmoodi-Meimand,
Kaushik Roy:
Data-retention flip-flops for power-down applications.
ISCAS (2) 2004: 677-680 |
| 179 | EE | Myeong-Eun Hwang,
Arijit Raychowdhury,
Kaushik Roy:
Effectiveness of energy recovery techniques in reducing on-chip power density in molecular nano-technologies.
ISCAS (3) 2004: 709-712 |
| 178 | EE | Hiroaki Suzuki,
Woopyo Jeong,
Kaushik Roy:
Low-power carry-select adder using adaptive supply voltage based on input vector patterns.
ISLPED 2004: 313-318 |
| 177 | EE | Hari Ananthan,
Chris H. Kim,
Kaushik Roy:
Larger-than-vdd forward body bias in sub-0.5V nanoscale CMOS.
ISLPED 2004: 8-13 |
| 176 | EE | Bipul Chandra Paul,
Arijit Raychowdhury,
Kaushik Roy:
Device optimization for ultra-low power digital sub-threshold operation.
ISLPED 2004: 96-101 |
| 175 | EE | Arijit Raychowdhury,
Kaushik Roy:
A Novel Multiple-Valued Logic Design Using Ballistic Carbon Nanotube FETs.
ISMVL 2004: 14-19 |
| 174 | EE | Swarup Bhunia,
Arijit Raychowdhury,
Kaushik Roy:
Frequency Specification Testing of Analog Filters Using Wavelet Transform of Dynamic Supply Current.
ISQED 2004: 389-394 |
| 173 | EE | Hari Ananthan,
Aditya Bansal,
Kaushik Roy:
FinFET SRAM - Device and Circuit Design Considerations.
ISQED 2004: 511-516 |
| 172 | EE | Kaushik Roy:
Low-Power Design.
ISQED 2004: 8 |
| 171 | EE | Dongku Kang,
Mark C. Johnson,
Kaushik Roy:
Simultaneous Multiple-Vdd Scheduling and Allocation for Partitioned Floorplan.
ISQED 2004: 98-103 |
| 170 | EE | Bipul Chandra Paul,
Cassondra Neau,
Kaushik Roy:
Impact of Body Bias on Delay Fault Testing of Nanoscale CMOS Circuits.
ITC 2004: 1269-1275 |
| 169 | EE | Arijit Raychowdhury,
Saibal Mukhopadhyay,
Kaushik Roy:
Modeling and Estimation of Leakage in Sub-90nm Devices.
VLSI Design 2004: 65- |
| 168 | EE | Naran Sirisantana,
Kaushik Roy:
Low-Power Design Using Multiple Channel Lengths and Oxide Thicknesses.
IEEE Design & Test of Computers 21(1): 56-63 (2004) |
| 167 | EE | Naran Sirisantana,
Bipul Chandra Paul,
Kaushik Roy:
Enhancing Yield at the End of the Technology Roadmap.
IEEE Design & Test of Computers 21(6): 563-571 (2004) |
| 166 | | Hai Li,
Swarup Bhunia,
Yiran Chen,
Kaushik Roy,
T. N. Vijaykumar:
DCG: deterministic clock-gating for low-power microprocessor design.
IEEE Trans. VLSI Syst. 12(3): 245-254 (2004) |
| 165 | EE | Arijit Raychowdhury,
Saibal Mukhopadhyay,
Kaushik Roy:
A circuit-compatible model of ballistic carbon nanotube field-effect transistors.
IEEE Trans. on CAD of Integrated Circuits and Systems 23(10): 1411-1420 (2004) |
| 2003 |
|---|
| 164 | EE | Saibal Mukhopadhyay,
Arijit Raychowdhury,
Kaushik Roy:
Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling.
DAC 2003: 169-174 |
| 163 | EE | Guoan Zhong,
Cheng-Kok Koh,
Venkataramanan Balakrishnan,
Kaushik Roy:
An adaptive window-based susceptance extraction and its efficient implementation.
DAC 2003: 728-731 |
| 162 | EE | Lih-Yih Chiou,
Swarup Bhunia,
Kaushik Roy:
Synthesis of Application-Specific Highly-Efficient Multi-Mode Systems for Low-Power Applications.
DATE 2003: 10096-10103 |
| 161 | EE | Hunsoo Choo,
Khurram Muhammad,
Kaushik Roy:
MRPF: An Architectural Transformation for Synthesis of High-Performance and Low-Power Digital Filters.
DATE 2003: 10700-10705 |
| 160 | EE | Amit Agarwal,
Kaushik Roy,
T. N. Vijaykumar:
Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology.
DATE 2003: 10778-10783 |
| 159 | EE | Seung Hoon Choi,
Kaushik Roy:
A New Crosstalk Noise Model for DOMINO Logic Circuits.
DATE 2003: 11112-11113 |
| 158 | EE | Naran Sirisantana,
Kaushik Roy:
Selectively Clocked CMOS Logic Style for Low-Power Noise-Immune Operations in Scaled Technologies.
DATE 2003: 11160-11161 |
| 157 | EE | Debjyoti Ghosh,
Swarup Bhunia,
Kaushik Roy:
Multiple Scan Chain Design Technique for Power Reduction during Test Application in BIST.
DFT 2003: 191-198 |
| 156 | EE | Hai Li,
Swarup Bhunia,
Yiran Chen,
T. N. Vijaykumar,
Kaushik Roy:
Deterministic Clock Gating for Microprocessor Power Reduction.
HPCA 2003: 113- |
| 155 | EE | Arijit Raychowdhury,
Saibal Mukhopadhyay,
Kaushik Roy:
Modeling of Ballistic Carbon Nanotube Field Effect Transistors for Efficient Circuit Simulation.
ICCAD 2003: 487-490 |
| 154 | EE | Hiroaki Suzuki,
Woopyo Jeong,
Kaushik Roy:
Low Power Adder with Adaptive Supply Voltage.
ICCD 2003: 103-106 |
| 153 | EE | Dongku Kang,
Mark C. Johnson,
Kaushik Roy:
Multiple-Vdd Scheduling/Allocation for Partitioned Floorplan.
ICCD 2003: 412-418 |
| 152 | EE | Yonghee Im,
Kaushik Roy:
A logic-aware layout methodology to enhance the noise immunity of domino circuits.
ISCAS (5) 2003: 637-640 |
| 151 | EE | Cassondra Neau,
Kaushik Roy:
Optimal body bias selection for leakage improvement and process compensation over different technology generations.
ISLPED 2003: 116-121 |
| 150 | EE | Saibal Mukhopadhyay,
Kaushik Roy:
Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation.
ISLPED 2003: 172-175 |
| 149 | EE | Amit Agarwal,
Kaushik Roy:
A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regime.
ISLPED 2003: 18-21 |
| 148 | EE | Yiran Chen,
Kaushik Roy,
Cheng-Kok Koh:
Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors.
ISLPED 2003: 229-234 |
| 147 | EE | Matthew Cooke,
Hamid Mahmoodi-Meimand,
Kaushik Roy:
Energy recovery clocking scheme and flip-flops for ultra low-energy applications.
ISLPED 2003: 54-59 |
| 146 | EE | Chris H. Kim,
Jae-Joon Kim,
Saibal Mukhopadhyay,
Kaushik Roy:
A forward body-biased low-leakage SRAM cache: device and architecture considerations.
ISLPED 2003: 6-9 |
| 145 | EE | Yonghee Im,
Kaushik Roy:
LALM: A Logic-Aware Layout Methodology to Enhance the Noise Immunity of Domino Circuits.
ISVLSI 2003: 45-54 |
| 144 | EE | Hai Li,
Chen-Yong Cher,
T. N. Vijaykumar,
Kaushik Roy:
VSV: L2-Miss-Driven Variable Supply-Voltage Scaling for Low Power.
MICRO 2003: 19-28 |
| 143 | EE | Rajiv V. Joshi,
Kaushik Roy:
Design of Deep Sub-Micron CMOS Circuits.
VLSI Design 2003: 15-16 |
| 142 | EE | Kaushik Roy,
T. M. Mak,
Kwang-Ting Cheng:
Embedded Tutorial: Test Consideration for Nanometer Scale CMOS Circuits.
VTS 2003: 313-318 |
| 141 | EE | Jongsun Park,
Khurram Muhammad,
Kaushik Roy:
High-performance FIR filter design based on sharing multiplication.
IEEE Trans. VLSI Syst. 11(2): 244-253 (2003) |
| 140 | EE | Saibal Mukhopadhyay,
Cassondra Neau,
R. T. Cakici,
Amit Agarwal,
Chris H. Kim,
Kaushik Roy:
Gate leakage reduction for scaled devices using transistor stacking.
IEEE Trans. VLSI Syst. 11(4): 716-730 (2003) |
| 139 | EE | Ali Keshavarzi,
Kaushik Roy,
Charles F. Hawkins,
Vivek De:
Multiple-parameter CMOS IC testing with increased sensitivity for IDDQ.
IEEE Trans. VLSI Syst. 11(5): 863-870 (2003) |
| 138 | EE | C. H.-I. Kim,
Hendrawan Soeleman,
Kaushik Roy:
Ultra-low-power DLMS adaptive filter for hearing aid applications.
IEEE Trans. VLSI Syst. 11(6): 1058-1067 (2003) |
| 137 | EE | Guoan Zhong,
Cheng-Kok Koh,
Kaushik Roy:
On-chip interconnect modeling by wire duplication.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(11): 1521-1532 (2003) |
| 2002 |
|---|
| 136 | EE | Shiyou Zhao,
Kaushik Roy,
Cheng-Kok Koh:
Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement.
ASP-DAC 2002: 489-498 |
| 135 | EE | Seung Hoon Choi,
Bipul Chandra Paul,
Kaushik Roy:
Dynamic Noise Analysis with Capacitive and Inductive Coupling.
ASP-DAC 2002: 65-70 |
| 134 | EE | Swarup Bhunia,
Hai Li,
Kaushik Roy:
A High Performance IDDQ Testable Cache for Scaled CMOS Technologies.
Asian Test Symposium 2002: 157- |
| 133 | EE | Swarup Bhunia,
Kaushik Roy,
Jaume Segura:
A novel wavelet transform based transient current analysis for fault detection and localization.
DAC 2002: 361-366 |
| 132 | EE | Amit Agarwal,
Hai Li,
Kaushik Roy:
DRG-cache: a data retention gated-ground cache for low power.
DAC 2002: 473-478 |
| 131 | EE | Seung Hoon Choi,
Kaushik Roy,
Florentin Dartu:
Timed pattern generation for noise-on-delay calculation.
DAC 2002: 870-873 |
| 130 | |
