| 2004 |
|---|
| 5 | EE | Masashi Shimanouchi:
Timing Accuracy Enhancement by a New Calibration Scheme for Multi-Gbps ATE.
ITC 2004: 567-576 |
| 4 | EE | A. T. Sivaram,
Masashi Shimanouchi,
Howard Maassen,
Robert Jackson:
Tester Architecture For The Source Synchronous Bus.
ITC 2004: 738-747 |
| 2003 |
|---|
| 3 | EE | Masashi Shimanouchi:
Periodic Jitter Injection with Direct Time Synthesis by SPPTM ATE for SerDes Jitter Tolerance Test in Production.
ITC 2003: 48-57 |
| 2002 |
|---|
| 2 | EE | Masashi Shimanouchi:
New Paradigm for Signal Paths in ATE Pin Electronics are Needed for Serialcom Device Testing.
ITC 2002: 903-912 |
| 2001 |
|---|
| 1 | | Masashi Shimanouchi:
An approach to consistent jitter modeling for various jitter aspects and measurement methods.
ITC 2001: 848-857 |
