Atsushi Takahashi

2008
30	EE	Yoichi Tomioka, Atsushi Takahashi: Routability driven modification method of monotonic via assignment for 2-layer Ball Grid Array packages. ASP-DAC 2008: 238-243
2007
29	EE	Yosuke Takahashi, Yukihide Kohira, Atsushi Takahashi: A fast clock scheduling for peak power reduction in LSI. ACM Great Lakes Symposium on VLSI 2007: 582-587
28	EE	Yukihide Kohira, Atsushi Takahashi: A Fast Register Relocation Method for Circuit Size Reduction in Generalized-Synchronous Framework. ISCAS 2007: 1795-1798
27	EE	Bakhtiar Affendi Rosdi, Atsushi Takahashi: Low Area Pipelined Circuits by the Replacement of Registers with Delay Elements. IEICE Transactions 90-A(12): 2736-2742 (2007)
26	EE	Yukihide Kohira, Atsushi Takahashi: Gate-Level Register Relocation in Generalized Synchronous Framework for Clock Period Minimization. IEICE Transactions 90-A(4): 800-807 (2007)
2006
25	EE	Bakhtiar Affendi Rosdi, Atsushi Takahashi: Replacement of Register with Delay Element for Reducing the Area of Pipelined Circuits. APCCAS 2006: 801-804
24	EE	Bakhtiar Affendi Rosdi, Atsushi Takahashi: Low area pipelined circuits by multi-clock cycle paths and clock scheduling. ASP-DAC 2006: 260-265
23	EE	Yoichi Tomioka, Atsushi Takahashi: Monotonic parallel and orthogonal routing for single-layer ball grid array packages. ASP-DAC 2006: 642-647
22	EE	Yukiko Kubo, Atsushi Takahashi: Global Routing by Iterative Improvements for Two-Layer Ball Grid Array Packages. IEEE Trans. on CAD of Integrated Circuits and Systems 25(4): 725-733 (2006)
21	EE	Bakhtiar Affendi Rosdi, Atsushi Takahashi: Multi-Clock Cycle Paths and Clock Scheduling for Reducing the Area of Pipelined Circuits. IEICE Transactions 89-A(12): 3435-3442 (2006)
20	EE	Yoichi Tomioka, Atsushi Takahashi: Routing of Monotonic Parallel and Orthogonal Netlists for Single-Layer Ball Grid Array Packages. IEICE Transactions 89-A(12): 3551-3559 (2006)
19	EE	Atsushi Takahashi: Practical Fast Clock-Schedule Design Algorithms. IEICE Transactions 89-A(4): 1005-1011 (2006)
2005
18	EE	Yukiko Kubo, Atsushi Takahashi: A global routing method for 2-layer ball grid array packages. ISPD 2005: 36-43
17	EE	Yukihide Kohira, Atsushi Takahashi: Clock Period Minimization Method of Semi-Synchronous Circuits by Delay Insertion. IEICE Transactions 88-A(4): 892-898 (2005)
16	EE	Yukiko Kubo, Atsushi Takahashi: A Via Assignment and Global Routing Method for 2-Layer Ball Grid Array Packages. IEICE Transactions 88-A(5): 1283-1289 (2005)
2004
15		Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahashi, Majid Sarrafzadeh: Incremental Timing Budget Management in Programmable Systems. ERSA 2004: 240-246
14	EE	Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahashi, Majid Sarrafzadeh: Optimal integer delay-budget assignment on directed acyclic graphs. IEEE Trans. on CAD of Integrated Circuits and Systems 23(8): 1184-1199 (2004)
2003
13	EE	Elaheh Bozorgzadeh, Soheil Ghiasi, Atsushi Takahashi, Majid Sarrafzadeh: Optimal integer delay budgeting on directed acyclic graphs. DAC 2003: 920-925
12	EE	Yusuke Maeda, Atsushi Takahashi, Takayuki Hara, Tamio Arai: Human-robot cooperative rope turning--an example of mechanical coordination through rhythm entrainment. Advanced Robotics 17(1): 67-78 (2003)
2001
11	EE	Makoto Saitoh, Masaaki Azuma, Atsushi Takahashi: Clustering based fast clock scheduling for light clock-tree. DATE 2001: 240-245
10		Yusuke Maeda, Atsushi Takahashi, Takayuki Hara, Tamio Arai: Human-Robot Cooperation with Mechanical Interaction Based on Rhythm Entrainment -Realization of Cooperative Rope Turning. ICRA 2001: 3477-3482
2000
9	EE	Masahiko Toyonaga, Keiichi Kurokawa, Takuya Yasui, Atsushi Takahashi: A practical clock tree synthesis for semi-synchronous circuits. ISPD 2000: 159-164
8		Yoji Kajitani, Atsushi Takahashi, Kengo R. Azegami, Shigetoshi Nakatake: Partition, Packing and Clock Distribution-A New Paradigm of Physical Design. VLSI Design 2000: 11
1999
7	EE	Tomoyuki Yoda, Atsushi Takahashi, Yoji Kajitani: Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion. ASP-DAC 1999: 125-
6	EE	Kengo R. Azegami, Atsushi Takahashi, Y. Kajitan: Enumerating the min-cuts for applications to graph extraction under size constraints. ISCAS (6) 1999: 174-177
1998
5		Tomonori Izumi, Atsushi Takahashi, Yoji Kajitani: Air-Pressure-Model-Based Fast Algorithms for General Floorplan. ASP-DAC 1998: 563-570
1997
4	EE	Atsushi Takahashi, Kazunori Inoue, Yoji Kajitani: Clock-tree routing realizing a clock-schedule for semi-synchronous circuits. ICCAD 1997: 260-265
1995
3	EE	Atsushi Takahashi, Shuichi Ueno, Yoji Kajitani: Mixed Searching and Proper-Path-Width. Theor. Comput. Sci. 137(2): 253-268 (1995)
1994
2	EE	Atsushi Takahashi, Shuichi Ueno, Yoji Kajitani: Minimal acyclic forbidden minors for the family of graphs with bounded path-width. Discrete Mathematics 127(1-3): 293-304 (1994)
1991
1		Atsushi Takahashi, Shuichi Ueno, Yoji Kajitani: Mixed-Searching and Proper-Path-Width. ISA 1991: 61-71

Coauthor Index

1	Tamio Arai	[10] [12]
2	Kengo R. Azegami	[6] [8]
3	Masaaki Azuma	[11]
4	Elaheh Bozorgzadeh (Eli Bozorgzadeh)	[13] [14] [15]
5	Soheil Ghiasi	[13] [14] [15]
6	Takayuki Hara	[10] [12]
7	Kazunori Inoue	[4]
8	Tomonori Izumi	[5]
9	Y. Kajitan	[6]
10	Yoji Kajitani	[1] [2] [3] [4] [5] [7] [8]
11	Yukihide Kohira	[17] [26] [28] [29]
12	Yukiko Kubo	[16] [18] [22]
13	Keiichi Kurokawa	[9]
14	Yusuke Maeda	[10] [12]
15	Shigetoshi Nakatake	[8]
16	Bakhtiar Affendi Rosdi	[21] [24] [25] [27]
17	Makoto Saitoh	[11]
18	Majid Sarrafzadeh	[13] [14] [15]
19	Yosuke Takahashi	[29]
20	Yoichi Tomioka	[20] [23] [30]
21	Masahiko Toyonaga	[9]
22	Shuichi Ueno	[1] [2] [3]
23	Takuya Yasui	[9]
24	Tomoyuki Yoda	[7]

Colors in the list of coauthors