| 2008 |
|---|
| 128 | EE | Pablo Viana,
Ann Gordon-Ross,
Edna Barros,
Frank Vahid:
A table-based method for single-pass cache optimization.
ACM Great Lakes Symposium on VLSI 2008: 71-76 |
| 127 | EE | Scott Sirowy,
Greg Stitt,
Frank Vahid:
C is for circuits: capturing FPGA circuits as sequential code for portability.
FPGA 2008: 117-126 |
| 126 | EE | David Sheldon,
Frank Vahid:
A pipelined binary tree as a case study on designing efficient circuits for an FPGA in a bram aware design.
FPGA 2008: 264 |
| 2007 |
|---|
| 125 | EE | Greg Stitt,
Frank Vahid:
Thread warping: a framework for dynamic synthesis of thread accelerators.
CODES+ISSS 2007: 93-98 |
| 124 | EE | Ann Gordon-Ross,
Frank Vahid:
A Self-Tuning Configurable Cache.
DAC 2007: 234-237 |
| 123 | EE | Scott Sirowy,
Yonghui Wu,
Stefano Lonardi,
Frank Vahid:
Two-level microprocessor-accelerator partitioning.
DATE 2007: 313-318 |
| 122 | EE | Scott Sirowy,
Yonghui Wu,
Stefano Lonardi,
Frank Vahid:
Clock-frequency assignment for multiple clock domain systems-on-a-chip.
DATE 2007: 397-402 |
| 121 | EE | Ann Gordon-Ross,
Pablo Viana,
Frank Vahid,
Walid A. Najjar,
Edna Barros:
A one-shot configurable-cache tuner for improved energy and performance.
DATE 2007: 755-760 |
| 120 | EE | David Sheldon,
Frank Vahid,
Stefano Lonardi:
Interactive presentation: Soft-core processor customization using the design of experiments paradigm.
DATE 2007: 821-826 |
| 119 | EE | Scott Sirowy,
Frank Vahid:
Integrated Coupling and Clock Frequency Assignment of Accelerators During Hardware/Software Partitioning.
IESS 2007: 145-154 |
| 118 | EE | Greg Stitt,
Frank Vahid:
Binary synthesis.
ACM Trans. Design Autom. Electr. Syst. 12(3): (2007) |
| 117 | EE | Greg Stitt,
Frank Vahid:
A Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms
CoRR abs/0710.4700: (2007) |
| 116 | EE | Roman L. Lysecky,
Frank Vahid:
A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning
CoRR abs/0710.4705: (2007) |
| 115 | EE | Ryan Mannion,
Harry Hsieh,
Susan Cotterell,
Frank Vahid:
System Synthesis for Networks of Programmable Blocks
CoRR abs/0710.4798: (2007) |
| 114 | EE | Frank Vahid:
It's Time to Stop Calling Circuits "Hardware".
IEEE Computer 40(9): 106-108 (2007) |
| 2006 |
|---|
| 113 | EE | Pablo Viana,
Ann Gordon-Ross,
Eamonn J. Keogh,
Edna Barros,
Frank Vahid:
Configurable cache subsetting for fast cache tuning.
DAC 2006: 695-700 |
| 112 | EE | David Sheldon,
Rakesh Kumar,
Roman L. Lysecky,
Frank Vahid,
Dean M. Tullsen:
Application-specific customization of parameterized FPGA soft-core processors.
ICCAD 2006: 261-268 |
| 111 | EE | David Sheldon,
Rakesh Kumar,
Frank Vahid,
Dean M. Tullsen,
Roman L. Lysecky:
Conjoining soft-core FPGA processors.
ICCAD 2006: 694-701 |
| 110 | EE | Greg Stitt,
Frank Vahid,
Walid A. Najjar:
A code refinement methodology for performance-improved synthesis from C.
ICCAD 2006: 716-723 |
| 109 | EE | Susan Lysecky,
Frank Vahid:
Automated Application-Specific Tuning of Parameterized Sensor-Based Embedded System Building Blocks.
Ubicomp 2006: 507-524 |
| 108 | EE | Susan Lysecky,
Frank Vahid:
Automated Generation of Basic Custom Sensor-Based Embedded Computing Systems Guided by End-User Optimization Criteria.
Ubicomp 2006: 69-86 |
| 107 | EE | Roman L. Lysecky,
Greg Stitt,
Frank Vahid:
Warp Processors.
ACM Trans. Design Autom. Electr. Syst. 11(3): 659-681 (2006) |
| 2005 |
|---|
| 106 | EE | Ann Gordon-Ross,
Frank Vahid,
Nikil Dutt:
A first look at the interplay of code reordering and configurable caches.
ACM Great Lakes Symposium on VLSI 2005: 416-421 |
| 105 | EE | Susan Cotterell,
Frank Vahid:
A logic block enabling logic configuration by non-experts in sensor networks.
CHI Extended Abstracts 2005: 1925-1928 |
| 104 | EE | Greg Stitt,
Frank Vahid,
Gordon McGregor,
Brian Einloth:
Hardware/software partitioning of software binaries: a case study of H.264 decode.
CODES+ISSS 2005: 285-290 |
| 103 | EE | Roman L. Lysecky,
Frank Vahid:
A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning.
DATE 2005: 18-23 |
| 102 | EE | Greg Stitt,
Frank Vahid:
A Decompilation Approach to Partitioning Software for Microprocessor/FPGA Platforms.
DATE 2005: 396-397 |
| 101 | EE | Ryan Mannion,
Harry Hsieh,
Susan Cotterell,
Frank Vahid:
System Synthesis for Networks of Programmable Blocks.
DATE 2005: 888-893 |
| 100 | EE | Roman L. Lysecky,
Frank Vahid,
Sheldon X.-D. Tan:
A Study of the Scalability of On-Chip Routing for Just-in-Time FPGA Compilation.
FCCM 2005: 57-62 |
| 99 | EE | Greg Stitt,
Zhi Guo,
Walid A. Najjar,
Frank Vahid:
Techniques for synthesizing binaries to an advanced register/memory structure.
FPGA 2005: 118-124 |
| 98 | EE | Roman L. Lysecky,
Kris Miller,
Frank Vahid,
Kees A. Vissers:
Firm-core Virtual FPGA for Just-in-Time FPGA Compilation (abstract only).
FPGA 2005: 271 |
| 97 | | Greg Stiff,
Frank Vahid:
New decompilation techniques for binary-level co-processor generation.
ICCAD 2005: 547-554 |
| 96 | EE | Susan Cotterell,
Ryan Mannion,
Frank Vahid,
Harry Hsieh:
eBlocks - an enabling technology for basic sensor based systems.
IPSN 2005: 422-427 |
| 95 | EE | Ann Gordon-Ross,
Frank Vahid,
Nikil D. Dutt:
Fast configurable-cache tuning with a unified second-level cache.
ISLPED 2005: 323-326 |
| 94 | EE | Chuanjun Zhang,
Frank Vahid,
Walid A. Najjar:
A highly configurable cache for low energy embedded systems.
ACM Trans. Embedded Comput. Syst. 4(2): 363-387 (2005) |
| 93 | EE | Ann Gordon-Ross,
Frank Vahid:
Frequent Loop Detection Using Efficient Nonintrusive On-Chip Hardware.
IEEE Trans. Computers 54(10): 1203-1215 (2005) |
| 92 | EE | Chuanjun Zhang,
Frank Vahid,
Jun Yang,
Walid A. Najjar:
A way-halting cache for low-energy high-performance systems.
TACO 2(1): 34-54 (2005) |
| 2004 |
|---|
| 91 | EE | Roman L. Lysecky,
Frank Vahid,
Sheldon X.-D. Tan:
Dynamic FPGA routing for just-in-time FPGA compilation.
DAC 2004: 954-959 |
| 90 | EE | Chuanjun Zhang,
Frank Vahid,
Roman L. Lysecky:
A Self-Tuning Cache Architecture for Embedded Systems.
DATE 2004: 142-147 |
| 89 | EE | Ann Gordon-Ross,
Frank Vahid,
Nikil Dutt:
Automatic Tuning of Two-Level Caches to Embedded Applications.
DATE 2004: 208-213 |
| 88 | EE | Chuanjun Zhang,
Jun Yang,
Frank Vahid:
Low Static-Power Frequent-Value Data Caches.
DATE 2004: 214-219 |
| 87 | EE | Chuanjun Zhang,
Frank Vahid:
Using a Victim Buffer in an Application-Specific Memory Hierarchy.
DATE 2004: 220-227 |
| 86 | EE | Roman L. Lysecky,
Frank Vahid:
A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning.
DATE 2004: 480-485 |
| 85 | EE | Zhi Guo,
Walid A. Najjar,
Frank Vahid,
Kees A. Vissers:
A quantitative analysis of the speedup factors of FPGAs over processors.
FPGA 2004: 162-170 |
| 84 | EE | Chuanjun Zhang,
Frank Vahid,
Jun Yang,
Walid A. Najjar:
A way-halting cache for low-energy high-performance systems.
ISLPED 2004: 126-131 |
| 83 | EE | Greg Stitt,
Frank Vahid,
Shawn Nematbakhsh:
Energy savings and speedups from partitioning critical software loops to hardware in embedded systems.
ACM Trans. Embedded Comput. Syst. 3(1): 218-232 (2004) |
| 82 | EE | Chuanjun Zhang,
Frank Vahid,
Roman L. Lysecky:
A self-tuning cache architecture for embedded systems.
ACM Trans. Embedded Comput. Syst. 3(2): 407-425 (2004) |
| 81 | | Roman L. Lysecky,
Susan Cotterell,
Frank Vahid:
A fast on-chip profiler memory using a pipelined binary tree.
IEEE Trans. VLSI Syst. 12(1): 120-122 (2004) |
| 2003 |
|---|
| 80 | EE | Ann Gordon-Ross,
Frank Vahid:
Frequent loop detection using efficient non-intrusive on-chip hardware.
CASES 2003: 117-124 |
| 79 | EE | Roman L. Lysecky,
Frank Vahid:
A codesigned on-chip logic minimizer.
CODES+ISSS 2003: 109-113 |
| 78 | EE | Susan Cotterell,
Frank Vahid,
Walid A. Najjar,
Harry Hsieh:
First results with eBlocks: embedded systems building blocks.
CODES+ISSS 2003: 168-175 |
| 77 | EE | Greg Stitt,
Roman L. Lysecky,
Frank Vahid:
Dynamic hardware/software partitioning: a first approach.
DAC 2003: 250-255 |
| 76 | EE | Roman L. Lysecky,
Frank Vahid:
On-chip logic minimization.
DAC 2003: 334-337 |
| 75 | EE | Chuanjun Zhang,
Frank Vahid:
Cache Configuration Exploration on Prototyping Platforms.
IEEE International Workshop on Rapid System Prototyping 2003: 164- |
| 74 | EE | Chuanjun Zhang,
Frank Vahid,
Walid A. Najjar:
A Highly-Configurable Cache Architecture for Embedded Systems.
ISCA 2003: 136-146 |
| 73 | EE | Chuanjun Zhang,
Frank Vahid,
Walid A. Najjar:
Energy Benefits of a Configurable Line Size Cache for Embedded Systems.
ISVLSI 2003: 87-91 |
| 72 | EE | Dinesh C. Suresh,
Walid A. Najjar,
Frank Vahid,
Jason R. Villarreal,
Greg Stitt:
Profiling tools for hardware/software partitioning of embedded applications.
LCTES 2003: 189-198 |
| 71 | EE | Frank Vahid:
Embedded System Design: UCR's Undergraduate Three-Course Sequence.
MSE 2003: 72-73 |
| 70 | EE | Ann Gordon-Ross,
Susan Cotterell,
Frank Vahid:
Tiny instruction caches for low power embedded systems.
ACM Trans. Embedded Comput. Syst. 2(4): 449-481 (2003) |
| 69 | EE | Chuanjun Zhang,
Frank Vahid,
Jun Yang,
Walid A. Najjar:
A Way-Halting Cache for Low-Energy High-Performance Systems.
Computer Architecture Letters 2: (2003) |
| 68 | EE | Frank Vahid:
The Softening of Hardware.
IEEE Computer 36(4): 27-34 (2003) |
| 67 | | Frank Vahid:
Making the Best of Those Extra Transistors.
IEEE Design & Test of Computers 20(1): 96- (2003) |
| 66 | EE | Frank Vahid,
Roman L. Lysecky,
Chuanjun Zhang,
Greg Stitt:
Highly configurable platforms for embedded computing systems.
Microelectronics Journal 34(11): 1025-1029 (2003) |
| 2002 |
|---|
| 65 | EE | Brian Grattan,
Greg Stitt,
Frank Vahid:
Codesign-extended applications.
CODES 2002: 1-6 |
| 64 | EE | Roman L. Lysecky,
Susan Cotterell,
Frank Vahid:
A fast on-chip profiler memory.
DAC 2002: 28-33 |
| 63 | EE | Greg Stitt,
Brian Grattan,
Jason R. Villarreal,
Frank Vahid:
Using On-Chip Configurable Logic to Reduce Embedded System Software Energy.
FCCM 2002: 143-151 |
| 62 | EE | Greg Stitt,
Frank Vahid:
Hardware/software partitioning of software binaries.
ICCAD 2002: 164-170 |
| 61 | EE | Susan Cotterell,
Frank Vahid:
Synthesis of customized loop caches for core-based embedded systems.
ICCAD 2002: 655-662 |
| 60 | EE | Ann Gordon-Ross,
Frank Vahid:
Dynamic Loop Caching Meets Preloaded Loop Caching - A Hybrid Approach.
ICCD 2002: 446-449 |
| 59 | EE | Chuanjun Zhang,
Frank Vahid:
A power-configurable bus for embedded systems.
ISCAS (5) 2002: 809-812 |
| 58 | EE | Frank Vahid,
Susan Cotterell:
Tuning of Loop Cache Architectures to Programs in Embedded System Design.
ISSS 2002: 8-13 |
| 57 | EE | Roman L. Lysecky,
Frank Vahid:
Prefetching for improved bus wrapper performance in cores.
ACM Trans. Design Autom. Electr. Syst. 7(1): 58-90 (2002) |
| 56 | EE | Frank Vahid:
Partitioning sequential programs for CAD using a three-step approach.
ACM Trans. Design Autom. Electr. Syst. 7(3): 413-429 (2002) |
| 55 | EE | Ann Gordon-Ross,
Susan Cotterell,
Frank Vahid:
Exploiting Fixed Programs in Embedded Systems: A Loop Cache Example.
Computer Architecture Letters 1: (2002) |
| 54 | EE | Greg Stitt,
Frank Vahid:
Energy Advantages of Microprocessor Platforms with On-Chip Configurable Logic.
IEEE Design & Test of Computers 19(6): 36-43 (2002) |
| 53 | EE | Tony Givargis,
Frank Vahid,
Jörg Henkel:
System-level exploration for Pareto-optimal configurations in parameterized system-on-a-chip.
IEEE Trans. VLSI Syst. 10(4): 416-422 (2002) |
| 52 | EE | Tony Givargis,
Frank Vahid,
Jörg Henkel:
Instruction-based system-level power evaluation of system-on-a-chip peripheral cores.
IEEE Trans. VLSI Syst. 10(6): 856-863 (2002) |
| 51 | EE | Tony Givargis,
Frank Vahid:
Platune: a tuning framework for system-on-a-chip platforms.
IEEE Trans. on CAD of Integrated Circuits and Systems 21(11): 1317-1327 (2002) |
| 50 | EE | Frank Vahid,
Tony Givargis,
Susan Cotterell:
Power Estimator Development for Embedded System Memory Tuning.
Journal of Circuits, Systems, and Computers 11(5): 459-476 (2002) |
| 2001 |
|---|
| 49 | EE | Tony Givargis,
Frank Vahid,
Jörg Henkel:
Trace-driven system-level power evaluation of system-on-a-chip peripheral cores.
ASP-DAC 2001: 306-312 |
| 48 | EE | Tony Givargis,
Frank Vahid,
Jörg Henkel:
System-Level Exploration for Pareto-Optimal Configurations in Parameterized Systems-on-a-Chip.
ICCAD 2001: 25-30 |
| 47 | EE | Frank Vahid,
Ann Gordon-Ross:
A self-optimizing embedded microprocessor using a loop table for low power.
ISLPED 2001: 219-224 |
| 46 | EE | Frank Vahid,
Tony Givargis:
Platform Tuning for Embedded Systems Design.
IEEE Computer 34(3): 112-114 (2001) |
| 45 | EE | T. D. Givargis,
Frank Vahid,
Jörg Henkel:
Evaluating power consumption of parameterized cache and bus architectures in system-on-a-chip designs.
IEEE Trans. VLSI Syst. 9(4): 500-508 (2001) |
| 44 | EE | Frank Vahid,
Rilesh Patel,
Greg Stitt:
Propagating constants past software to hardware peripherals in fixed-application embedded systems.
SIGARCH Computer Architecture News 29(5): 25-30 (2001) |
| 2000 |
|---|
| 43 | | Frank Vahid,
Jan Madsen:
Proceedings of the Eighth International Workshop on Hardware/Software Codesign, CODES 2000, San Diego, California, USA, 2000
ACM 2000 |
| 42 | EE | Tony Givargis,
Frank Vahid,
Jörg Henkel:
A hybrid approach for core-based system-level power modeling.
ASP-DAC 2000: 141-146 |
| 41 | EE | Greg Stitt,
Frank Vahid,
Tony Givargis,
Roman L. Lysecky:
A first-step towards an architecture tuning methodology for low power.
CASES 2000: 187-192 |
| 40 | EE | Tony Givargis,
Frank Vahid:
Parameterized system design.
CODES 2000: 98-102 |
| 39 | EE | Jörg Henkel,
Tony Givargis,
Frank Vahid:
Fast Cache and Bus Power Estimation for Parameterized System-on-a-Chip Design.
DATE 2000: 333- |
| 38 | EE | Roman L. Lysecky,
Frank Vahid,
Tony Givargis:
Techniques for Reducing Read Latency of Core Bus Wrappers.
DATE 2000: 84-91 |
| 37 | EE | Tony Givargis,
Frank Vahid,
Jörg Henkel:
Instruction-based System-level Power Evaluation of System-On-A-Chip Peripheral Cores.
ISSS 2000: 163-171 |
| 36 | EE | Roman L. Lysecky,
Frank Vahid,
Tony Givargis:
Experiments with the Peripheral Virtual Component Interface.
ISSS 2000: 221-224 |
| 1999 |
|---|
| 35 | | Ahmed Amine Jerraya,
Luciano Lavagno,
Frank Vahid:
Proceedings of the Seventh International Workshop on Hardware/Software Codesign, CODES 1999, Rome, Italy, 1999
ACM 1999 |
| 34 | EE | Frank Vahid,
Tony Givargis:
The case for a configure-and-execute paradigm.
CODES 1999: 59-63 |
| 33 | EE | Enoch Hwang,
Frank Vahid,
Yu-Chin Hsu:
FSMD Functional Partitioning for Low Power.
DATE 1999: 22-27 |
| 32 | EE | Tony Givargis,
Jörg Henkel,
Frank Vahid:
Interface and cache power exploration for core-based embedded system design.
ICCAD 1999: 270-273 |
| 31 | EE | Roman L. Lysecky,
Frank Vahid,
Rilesh Patel,
Tony Givargis:
Pre-Fetching for Improved Core Interfacing.
ISSS 1999: 51-55 |
| 30 | EE | Frank Vahid:
Procedure cloning: a transformation for improved system-level functional partitioning.
ACM Trans. Design Autom. Electr. Syst. 4(1): 70-96 (1999) |
| 29 | EE | Frank Vahid:
Techniques for minimizing and balancing I/O during functional partitioning.
IEEE Trans. on CAD of Integrated Circuits and Systems 18(1): 69-75 (1999) |
| 1998 |
|---|
| 28 | EE | Daniel Gajski,
Frank Vahid,
Sanjiv Narayan,
Jie Gong:
System-level exploration with SpecSyn.
DAC 1998: 812-817 |
| 27 | EE | Tony Givargis,
Frank Vahid:
Interface Exploration for Reduced Power in Core-Based Systems.
ISSS 1998: 117-124 |
| 26 | EE | Frank Vahid:
A Three-Step Approach to the Functional Partitioning of Large Behavioral Processes.
ISSS 1998: 152-157 |
| 25 | EE | Frank Vahid,
Tony Givargis:
Incorporating Cores into System-Level Specification.
ISSS 1998: 43-50 |
| 24 | EE | Frank Vahid,
Thuy Dm Le,
Yu-Chin Hsu:
Functional partitioning improvements over structural partitioning for packaging constraints and synthesis: tool performance.
ACM Trans. Design Autom. Electr. Syst. 3(2): 181-208 (1998) |
| 23 | EE | Daniel D. Gajski,
Frank Vahid,
Sanjiv Narayan,
Jie Gong:
SpecSyn: an environment supporting the specify-explore-refine paradigm for hardware/software system design.
IEEE Trans. VLSI Syst. 6(1): 84-100 (1998) |
| 1997 |
|---|
| 22 | EE | Frank Vahid:
Modifying Min-Cut for Hardware and Software Functional Partitioning.
CODES 1997: 43-48 |
| 21 | EE | Frank Vahid,
Linus Tauro:
An Object-Oriented Communication Library for Hardware-Software CoDesign.
CODES 1997: 81-86 |
| 20 | EE | Frank Vahid:
I/O and Performance Tradeoffs with the FunctionBus During Multi-FPGA Partitioning.
FPGA 1997: 27-34 |
| 19 | EE | Frank Vahid:
Port Calling: A Transformation for Reducing I/O during Multi-Package Functional Partitioning.
ISSS 1997: 107-112 |
| 1996 |
|---|
| 18 | EE | Frank Vahid,
Thuy Dm Le:
Towards a Model for Hardware and Software Functional Partitioning.
CODES 1996: 116-123 |
| 17 | EE | Frank Vahid,
Thuy Dm Le,
Yu-Chin Hsu:
A Comparison of Functional and Structural Partitioning.
ISSS 1996: 121-126 |
| 16 | EE | Daniel D. Gajski,
Sanjiv Narayan,
Loganath Ramachandran,
Frank Vahid,
Peter Fung:
System design methodologies: aiming at the 100 h design cycle.
IEEE Trans. VLSI Syst. 4(1): 70-82 (1996) |
| 1995 |
|---|
| 15 | EE | Frank Vahid,
Daniel D. Gajski:
Closeness metrics for system-level functional partitioning.
EURO-DAC 1995: 328-333 |
| 14 | EE | Frank Vahid:
Procedure exlining: a new system-level specification transformation.
EURO-DAC 1995: 508-513 |
| 13 | EE | Frank Vahid,
Daniel D. Gajski:
Clustering for improved system-level functional partitioning.
ISSS 1995: 28-35 |
| 12 | EE | Frank Vahid:
Procedure exlining: a transformation for improved system and behavioral synthesis.
ISSS 1995: 84-89 |
| 11 | EE | Daniel D. Gajski,
Frank Vahid:
Specification and Design of Embedded Hardware-Software Systems.
IEEE Design & Test of Computers 12(1): 53-67 (1995) |
| 10 | EE | Frank Vahid,
Daniel D. Gajski:
Incremental hardware estimation during hardware/software functional partitioning.
IEEE Trans. VLSI Syst. 3(3): 459-464 (1995) |
| 9 | EE | Frank Vahid,
Sanjiv Narayan,
Daniel D. Gajski:
SpecCharts: a VHDL front-end for embedded systems.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(6): 694-706 (1995) |
| 1994 |
|---|
| 8 | | Daniel Gajski,
Frank Vahid,
Sanjiv Narayan:
A System-Design Methodology: Executable-Specification Refinement.
EDAC-ETC-EUROASIC 1994: 458-463 |
| 7 | EE | Loganath Ramachandran,
Daniel D. Gajski,
Sanjiv Narayan,
Frank Vahid,
Peter Fung:
100-hour design cycle: a test case.
EURO-DAC 1994: 144-149 |
| 6 | EE | Frank Vahid,
Daniel D. Gajski,
Jie Gong:
A binary-constraint search algorithm for minimizing hardware during hardware/software partitioning.
EURO-DAC 1994: 214-219 |
| 5 | EE | Frank Vahid,
Daniel D. Gajski,
Sanjiv Narayan:
A transformation for integrating VHDL behavioral specification with synthesis and software generation.
EURO-DAC 1994: 552-557 |
| 1992 |
|---|
| 4 | EE | Frank Vahid,
Daniel Gajski:
Specification Partitioning for System Design.
DAC 1992: 219-224 |
| 3 | EE | Sanjiv Narayan,
Frank Vahid,
Daniel D. Gajski:
System Specification with the SpecCharts Language.
IEEE Design & Test of Computers 9(4): 6-13 (1992) |
| 1991 |
|---|
| 2 | | Sanjiv Narayan,
Frank Vahid,
Daniel Gajski:
System Specification and Synthesis with the SpecCharts Language.
ICCAD 1991: 266-269 |
| 1 | | Frank Vahid,
Daniel Gajski:
Obtaining Functionally Equivalent Simulations using VHDL and a Time-Shift Transformation.
ICCAD 1991: 362-365 |
