Hideo Ito

2008
38	EE	Masato Kitakami, Bochuan Cai, Hideo Ito: A Checkpointing Method with Small Checkpoint Latency. IEICE Transactions 91-D(3): 857-861 (2008)
2007
37	EE	Takashi Ikeda, Kazuteru Namba, Hideo Ito: Soft Error Hardened Latch Scheme for Enhanced Scan Based Delay Fault Testing. DFT 2007: 282-290
36	EE	Abderrahim Doumar, Kentaroh Katoh, Hideo Ito: Fault Tolerant SoC Architecture Design for JPEG2000 Using Partial Reconfigurability. DFT 2007: 31-40
35	EE	Gang Zeng, Hideo Ito: Low-Cost IP Core Test Using Tri-Template-Based Codes. IEICE Transactions 90-D(1): 288-295 (2007)
2006
34	EE	Gang Zeng, Hideo Ito: Concurrent core test for SOC using shared test set and scan chain disable. DATE 2006: 1045-1050
33	EE	Gang Zeng, Youhua Shi, Toshinori Takabatake, Masao Yanagisawa, Hideo Ito: Low-Cost IP Core Test Using Multiple-Mode Loading Scan Chain and Scan Chain Clusters. DFT 2006: 136-144
32	EE	Yoichi Sasaki, Kazuteru Namba, Hideo Ito: Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit. DFT 2006: 327-335
31	EE	Kentaroh Katoh, Hideo Ito: Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices. European Test Symposium 2006: 69-74
30	EE	Gang Zeng, Hideo Ito: Concurrent Core Testing for SOC Using Merged Test Set and Scan Tree. IEICE Transactions 89-D(3): 1157-1164 (2006)
29	EE	Kazuteru Namba, Hideo Ito: Proposal of Testable Multi-Context FPGA Architecture. IEICE Transactions 89-D(5): 1687-1693 (2006)
28	EE	Kazuteru Namba, Hideo Ito: Redundant Design for Wallace Multiplier. IEICE Transactions 89-D(9): 2512-2524 (2006)
2005
27	EE	Gang Zeng, Hideo Ito: Concurrent Core Test for Test Cost Reduction Using Merged Test Set and Scan Tree. ICCD 2005: 143-146
26	EE	Kentaroh Katoh, Abderrahim Doumar, Hideo Ito: Design of On-Line Testing for SoC with IEEE P1500 Compliant Cores Using Reconfigurable Hardware and Scan Shift. IOLTS 2005: 203-204
25	EE	Kazuteru Namba, Hideo Ito: Design of Defect Tolerant Wallace Multiplier. PRDC 2005: 300-304
24	EE	Kazuteru Namba, Hideo Ito: Scan Design for Two-Pattern Test without Extra Latches. IEICE Transactions 88-D(12): 2777-2785 (2005)
23	EE	Gang Zeng, Hideo Ito: Hybrid Pattern BIST for Low-Cost Core Testing Using Embedded FPGA Core. IEICE Transactions 88-D(5): 984-992 (2005)
22	EE	Gang Zeng, Hideo Ito: X-Tolerant Test Data Compression for SOC with Enhanced Diagnosis Capability. IEICE Transactions 88-D(7): 1662-1670 (2005)
21	EE	Kazuteru Namba, Hideo Ito: Deterministic Delay Fault BIST Using Adjacency Test Pattern Generation. IEICE Transactions 88-D(9): 2135-2142 (2005)
2004
20	EE	Gang Zeng, Hideo Ito: Non-Intrusive Test Compression for SOC Using Embedded FPGA Core. DFT 2004: 413-421
19	EE	Manabu Sueishi, Masato Kitakami, Hideo Ito: Fault-Tolerant Message Switching Based on Wormhole Switching and Backtracking. PRDC 2004: 183-190
18	EE	Gang Zeng, Hideo Ito: Hybrid BIST for System-on-a-Chip Using an Embedded FPGA Core. VTS 2004: 355-360
2003
17	EE	Gang Zeng, Hideo Ito: Efficient Test Data Decompression for System-on-a-Chip Using an Embedded FPGA Core. DFT 2003: 503-510
16	EE	Abderrahim Doumar, Hideo Ito: Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey. IEEE Trans. VLSI Syst. 11(3): 386-405 (2003)
2002
15	EE	Lihong Tong, Kazuki Suzuki, Hideo Ito: Optimal Seed Generation for Delay Fault Detection BIST. Asian Test Symposium 2002: 116-121
14		Toshinori Takabatake, Masato Kitakami, Hideo Ito: A Fault-tolerant Routing Strategy for Generalized Hierarchical Completely-connected Networks. IASTED PDCS 2002: 619-624
13	EE	Toshinori Takabatake, Masato Kitakami, Hideo Ito: Fault-Tolerant Properties of Generalized Hierarchical Completely-Connected Networks. PRDC 2002: 137-144
2001
12	EE	Toshinori Takabatake, Masato Kitakami, Hideo Ito: Escape and Restoration Routing: Suspensive Deadlock Recovery in Interconnection Networks. PRDC 2001: 127-136
11	EE	Masato Kitakami, Shunji Kubota, Hideo Ito: Fault-Tolerance of Functional Programs Based on the Parallel Graph Reduction. PRDC 2001: 319-324
2000
10	EE	Abderrahim Doumar, Hideo Ito: Testing approach within FPGA-based fault tolerant systems. Asian Test Symposium 2000: 411-416
9	EE	Abderrahim Doumar, Hideo Ito: Design of Switching Blocks Tolerating Defects/Faults in FPGA Interconnection Resources. DFT 2000: 134-142
1999
8	EE	Abderrahim Doumar, Hideo Ito: Testing the Logic Cells and Interconnect Resources for FPGAs. Asian Test Symposium 1999: 369-374
7	EE	Abderrahim Doumar, Satoshi Kaneko, Hideo Ito: Defect and Fault Tolerance FPGAs by Shifting the Configuration Data. DFT 1999: 377-385
6	EE	Keiichi Kaneko, Hideo Ito: Fault-Tolerant Routing Algorithms for Hypercube Networks. IPPS/SPDP 1999: 218-224
5	EE	Toshinori Takabatake, Keiichi Kaneko, Hideo Ito: Generalized Hierarchical Completely-Connected Networks. ISPAN 1999: 68-73
4	EE	Mikio Yagi, Keiichi Kaneko, Hideo Ito: LLT and LTn Schemes: Error Recovery Schemes in Mobile Environments. PRDC 1999: 23-
3	EE	Abderrahim Doumar, Hideo Ito: An Automatic Testing and Diagnosis for FPGAs. PRDC 1999: 45-
1994
2		Hideo Ito, Takashi Yagi: Fault Tolerant Design Using Error Correcting Code for Multilayer Neural Networks. DFT 1994: 177-184
1993
1		Hideo Ito: A Defect-Tolerant Design for WSI Interconnection Networks and Its Application to Hypercube. DFT 1993: 80-87

Coauthor Index

1	Bochuan Cai	[38]
2	Abderrahim Doumar	[3] [7] [8] [9] [10] [16] [26] [36]
3	Takashi Ikeda	[37]
4	Keiichi Kaneko	[4] [5] [6]
5	Satoshi Kaneko	[7]
6	Kentaroh Katoh	[26] [31] [36]
7	Masato Kitakami	[11] [12] [13] [14] [19] [38]
8	Shunji Kubota	[11]
9	Kazuteru Namba	[21] [24] [25] [28] [29] [32] [37]
10	Yoichi Sasaki	[32]
11	Youhua Shi	[33]
12	Manabu Sueishi	[19]
13	Kazuki Suzuki	[15]
14	Toshinori Takabatake	[5] [12] [13] [14] [33]
15	Lihong Tong	[15]
16	Mikio Yagi	[4]
17	Takashi Yagi	[2]
18	Masao Yanagisawa	[33]
19	Gang Zeng	[17] [18] [20] [22] [23] [27] [30] [33] [34] [35]

Colors in the list of coauthors