| 2008 |
|---|
| 59 | EE | Konstantin Septinus,
Christian Grimm,
Vladislav Rumyantsev,
Peter Pirsch:
On the Benefit of Caching Traffic Flow Data in the Link Buffer.
SAMOS 2008: 2-11 |
| 2007 |
|---|
| 58 | EE | Guillermo Payá Vayá,
Javier Martín-Langerwerf,
Piriya Taptimthong,
Peter Pirsch:
Design Space Exploration of Media Processors: A Generic VLIW Architecture and a Parameterized Scheduler.
ARCS 2007: 254-267 |
| 57 | EE | Guillermo Paya-Vay,
Javier Martín-Langerwerf,
Peter Pirsch:
RAPANUI: A case study in Rapid Prototyping for Multiprocessor System-on-Chip.
DSD 2007: 215-221 |
| 56 | EE | Guillermo Payá Vayá,
Javier Martín-Langerwerf,
Piriya Taptimthong,
Peter Pirsch:
Design Space Exploration of Media Processors: A Parameterized Scheduler.
ICSAMOS 2007: 41-49 |
| 55 | EE | Holger Flatt,
Sebastian Hesselbarth,
Sebastian Flügel,
Peter Pirsch:
A Modular Coprocessor Architecture for Embedded Real-Time Image and Video Signal Processing.
SAMOS 2007: 241-250 |
| 54 | EE | Guillermo Payá Vayá,
Thomas Jambor,
Konstantin Septinus,
Sebastian Hesselbarth,
Holger Flatt,
Marc Freisfeld,
Peter Pirsch:
ChipDesign: from theory to real world.
WCAE 2007: 58-64 |
| 2005 |
|---|
| 53 | | Matthias Winter,
Peter Pirsch:
Von abstrakten Architekturtemplates zur hardwarenahen Architekturexploration.
GI Jahrestagung (1) 2005: 458 |
| 52 | EE | Guillermo Payá Vayá,
Javier Martín-Langerwerf,
Peter Pirsch:
RAPANUI: Rapid Prototyping for Media Processor Architecture Exploration.
SAMOS 2005: 32-40 |
| 51 | EE | Hans-Joachim Stolberg,
Mladen Berekovic,
Sören Moch,
Lars Friebe,
Mark Bernd Kulaczewski,
Sebastian Flügel,
Heiko Klußmann,
Andreas Dehnhardt,
Peter Pirsch:
HiBRID-SoC: A Multi-Core SoC Architecture for Multimedia Signal Processing.
VLSI Signal Processing 41(1): 9-20 (2005) |
| 50 | EE | Hans-Joachim Stolberg,
Mladen Berekovic,
Peter Pirsch:
A Platform-Independent Methodology for Performance Estimation of Multimedia Signal Processing Applications.
VLSI Signal Processing 41(2): 139-151 (2005) |
| 2004 |
|---|
| 49 | EE | Carsten Reuter,
Javier Martín-Langerwerf,
Hans-Joachim Stolberg,
Peter Pirsch:
Performance Estimation of Streaming Media Applications for Reconfigurable Platforms.
SAMOS 2004: 69-77 |
| 48 | EE | Sören Moch,
Mladen Berekovic,
Hans-Joachim Stolberg,
Lars Friebe,
Mark Bernd Kulaczewski,
Andreas Dehnhardt,
Peter Pirsch:
HIBRID-SOC: a multi-core architecture for image and video applications.
SIGARCH Computer Architecture News 32(3): 55-61 (2004) |
| 47 | EE | Mladen Berekovic,
Sören Moch,
Peter Pirsch:
A scalable, clustered SMT processor for digital signal processing.
SIGARCH Computer Architecture News 32(3): 62-69 (2004) |
| 2003 |
|---|
| 46 | EE | Hans-Joachim Stolberg,
Mladen Berekovic,
Lars Friebe,
Sören Moch,
Sebastian Flügel,
Xun Mao,
Mark Bernd Kulaczewski,
Heiko Klußmann,
Peter Pirsch:
HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing Applications.
DATE 2003: 20008-20013 |
| 45 | | Hans-Joachim Stolberg,
Mladen Berekovic,
Lars Friebe,
Sören Moch,
Sebastian Flügel,
Mark Bernd Kulaczewski,
Peter Pirsch:
HiBRID-SoC: a multi-core architecture for image and video applications.
ICIP (3) 2003: 101-104 |
| 44 | | Hans-Joachim Stolberg,
Mladen Berekovic,
Lars Friebe,
Sören Moch,
Mark Bernd Kulaczewski,
Peter Pirsch:
HiBRID-SoC: A Multi-Core System-on-Chip Architecture for Multimedia Signal Processing.
VLSI-SOC 2003: 155-160 |
| 2002 |
|---|
| 43 | EE | Peter Pirsch,
Achim Freimann,
C. Klar,
Jens Peter Wittenburg:
Processor Architectures for Multimedia Applications.
Embedded Processor Design Challenges 2002: 188-206 |
| 42 | EE | Javier Martín-Langerwerf,
Carsten Reuter,
Holger Kropp,
Peter Pirsch:
Benefits of Macro-Based Multi-FPGA Partitioning for Video Processing Applications.
IEEE International Workshop on Rapid System Prototyping 2002: 60-65 |
| 41 | | Xun Mao,
Wei Wang,
Huimin Gong,
Yan L. He,
Jian Lou,
Lu Yu,
Qingdong Yao,
Peter Pirsch:
Highly efficient simulation environment for HDTV video decoder in VLSI design.
VCIP 2002: 1006-1014 |
| 40 | | Mladen Berekovic,
Hans-Joachim Stolberg,
Peter Pirsch:
Multicore system-on-chip architecture for MPEG-4 streaming video.
IEEE Trans. Circuits Syst. Video Techn. 12(8): 688- (2002) |
| 39 | EE | Mladen Berekovic,
Peter Pirsch,
Thorsten Selinger,
Kai-Immo Wels,
Carolina Miro,
Anne Lafage,
Christoph Heer,
Giovanni Ghigo:
Architecture of an Image Rendering Co-Processor for MPEG-4 Visual Compositing.
VLSI Signal Processing 31(2): 157-171 (2002) |
| 2001 |
|---|
| 38 | EE | Hans-Joachim Stolberg,
Mladen Berekovic,
Peter Pirsch,
Holger Runge:
Implementing The MPEG-4 Advanced Simple Profile For Streaming Video Applications.
ICME 2001 |
| 37 | EE | Mark Bernd Kulaczewski,
Stefan Zimmerman,
Erich Barke,
Peter Pirsch:
CHIPDESIGN - A Novel Project-oriented Microelectronics Course.
MSE 2001: 71-72 |
| 36 | EE | Peter Pirsch,
Carsten Reuter,
Jens Peter Wittenburg,
Mark Bernd Kulaczewski,
Hans-Joachim Stolberg:
Architecture Concepts for Multimedia Signal Processing.
VLSI Signal Processing 29(3): 157-165 (2001) |
| 2000 |
|---|
| 35 | | Dimitrios Soudris,
Peter Pirsch,
Erich Barke:
Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation, 10th International Workshop, PATMOS 2000, Göttingen, Germany, September 13-15, 2000, Proceedings
Springer 2000 |
| 34 | EE | Mladen Berekovic,
Peter Pirsch,
Thorsten Selinger,
Kai-Immo Wels,
Carolina Miro,
Anne Lafage,
Christoph Heer,
Giovanni Ghigo:
Architecture of an Image Rendering Co-Processor for MPEG-4 Systems.
ASAP 2000: 15-24 |
| 33 | EE | Klaus Herrmann,
Sören Moch,
Jörg Hilgenstock,
Peter Pirsch:
Implementation of a Multiprocessor System with Distributed Embedded DRAM on a Large Area Integrated Circuit.
DFT 2000: 105-113 |
| 1999 |
|---|
| 32 | EE | Hans-Joachim Stolberg,
Martin Ohmacht,
Peter Pirsch:
Cellular Multiprocessor Arrays with Adaptive Resource Utilization.
ACPC 1999: 480-489 |
| 31 | | Jens Peter Wittenburg,
Willm Hinrichs,
Martin Ohmacht,
Hanno Lieske,
Helge Kloos,
Peter Pirsch:
HiPAR-DSP: Ein 1.3 GOPS Multimedia Signalprozessor.
ARCS 1999: 15-21 |
| 30 | | Helge Kloos,
Mladen Berekovic,
Peter Pirsch:
Hardware Realisierung einer JAVA Virtual Machine für High Performance Multimedia-Anwendungen.
ARCS 1999: 5-14 |
| 29 | | Holger Kropp,
Carsten Reuter,
Matthias Wiege,
Tien-Toan Do,
Peter Pirsch:
An FPGA-based Prototyping System for Real-Time Verification of Video Processing Schemes.
FPL 1999: 333-338 |
| 28 | EE | Jörg Hilgenstock,
Klaus Herrmann,
Peter Pirsch:
Memory Organization of a Single-Chip Video Signal Processing System with Embedded DRAM.
Great Lakes Symposium on VLSI 1999: 42-45 |
| 27 | EE | Mladen Berekovic,
K. Jacob,
Peter Pirsch:
Architecture of a hardware module for MPEG-4 shape decoding.
ISCAS (1) 1999: 157-160 |
| 26 | EE | Mladen Berekovic,
Helge Kloos,
Peter Pirsch:
Hardware Realization of a Java Virtual Machine for High Performance Multimedia Applications.
VLSI Signal Processing 22(1): 31-43 (1999) |
| 25 | EE | Mohammad Ibrahim,
Peter Pirsch,
Johan McCanny:
Guest Editors' Introduction.
VLSI Signal Processing 22(1): 5-6 (1999) |
| 24 | EE | Mladen Berekovic,
Hans-Joachim Stolberg,
Mark Bernd Kulaczewski,
Peter Pirsch,
Henning Möller,
Holger Runge,
Johannes Kneip,
Benno Stabernack:
Instruction Set Extensions for MPEG-4 Video.
VLSI Signal Processing 23(1): 27-49 (1999) |
| 1998 |
|---|
| 23 | EE | Mladen Berekovic,
Peter Pirsch:
An Array Processor Architecture with Parallel Data Cache for Image Rendering and Compositing.
Computer Graphics International 1998: 411- |
| 22 | EE | Jörg Hilgenstock,
Klaus Herrmann,
Jan Otterstedt,
Dirk Niggemeyer,
Peter Pirsch:
A Video Signal Processor for MIMD Multiprocessing.
DAC 1998: 50-55 |
| 21 | EE | Jens Peter Wittenburg,
Willm Hinrichs,
Johannes Kneip,
Martin Ohmacht,
Mladen Berekovic,
Hanno Lieske,
Helge Kloos,
Peter Pirsch:
Realization of a Programmable Parallel DSP for High Performance Image Processing Applications.
DAC 1998: 56-61 |
| 20 | EE | Tien-Toan Do,
Holger Kropp,
Carsten Reuter,
Peter Pirsch:
A Flexible Implementation of High-Performance FIR Filters on Xilinx FPGAs.
FPL 1998: 441-445 |
| 19 | EE | Holger Kropp,
Carsten Reuter,
Peter Pirsch:
The Video and Image Processing Emulation System VIPES.
International Workshop on Rapid System Prototyping 1998: 170-175 |
| 18 | EE | Mladen Berekovic,
Peter Pirsch,
Johannes Kneip:
An Algorithm-Hardware-System Approach to VLIW Multimedia Processors.
VLSI Signal Processing 20(1-2): 163-180 (1998) |
| 1997 |
|---|
| 17 | EE | Carsten Reuter,
Markus Schwiegershausen,
Peter Pirsch:
Heterogeneous Multiprocessor Scheduling and Allocation using Evolutionary Algorithms.
ASAP 1997: 294-303 |
| 16 | | Tien-Toan Do,
Holger Kropp,
Markus Schwiegershausen,
Peter Pirsch:
Implementation of pipelined multipliers on Xilinx FPGAs.
FPL 1997: 51-60 |
| 15 | EE | Johannes Kneip,
Mladen Berekovic,
Jens Peter Wittenburg,
Willm Hinrichs,
Peter Pirsch:
An Algorithm Adapted Autonomous Controlling Concept for a Parallel Single-Chip Digital Signal Processor.
VLSI Signal Processing 16(1): 31-40 (1997) |
| 1995 |
|---|
| 14 | EE | Markus Schwiegershausen,
Peter Pirsch:
A formal approach for the optimization of heterogeneous multiprocessors for complex image processing schemes.
EURO-DAC 1995: 8-13 |
| 13 | | Peter Pirsch,
Johannes Kneip,
Karsten Rönner:
Parallelization Resources of Image Processing Algorithms and Their Mapping on a Programmable Parallel Videosignal Processor.
ISCAS 1995: 562-565 |
| 12 | | Marco Winzker,
Peter Pirsch,
Jochen Reimers:
Architecture and Memory Requirements for Stand-Alone and Hierarchical MPEG2 HDTV-Decoders with Synchronous DRAMs.
ISCAS 1995: 609-612 |
| 11 | EE | Markus Schwiegershausen,
Peter Pirsch:
A system level design methodology for the optimization of heterogeneous multiprocessors.
ISSS 1995: 162-169 |
| 10 | EE | Mirjam Schönfeld,
Jens Franzen,
Markus Schwiegershausen,
Peter Pirsch,
Uwe Vehlies,
Andreas Münzner:
The LISA design environment for the synthesis of array processors including memories for the data transfer and fault tolerance by reconfiguration and coding techniques.
VLSI Signal Processing 11(1-2): 51-74 (1995) |
| 1993 |
|---|
| 9 | | Klaus Gaedke,
Jens Franzen,
Peter Pirsch:
A Fault-tolerant DCT-Architecture Based on Distributed Arithmetic.
ISCAS 1993: 1583-1586 |
| 8 | | Peter Pirsch,
W. Gehrke,
R. Hoffer:
A Hierarchical Multiprocessor Achitecture for Video Coding Applications.
ISCAS 1993: 1750-1753 |
| 7 | | J. Schönfeld,
Peter Pirsch:
Single board image processing unit for vehicle guidance.
VLSI 1993: 151-160 |
| 6 | EE | V. Hecht,
Karsten Rönner,
Peter Pirsch:
A defect-tolerant systolic array implementation for real time image processing.
VLSI Signal Processing 5(1): 37-47 (1993) |
| 5 | EE | Klaus Gaedke,
Hartwig Jeschke,
Peter Pirsch:
A VLSI based MIMD architecture of a multiprocessor system for real-time video processing applications.
VLSI Signal Processing 5(2-3): 159-169 (1993) |
| 1991 |
|---|
| 4 | | Mirjam Schönfeld,
Markus Schwiegershausen,
Peter Pirsch:
Synthesis of intermediate memories for the data supply to processor arrays.
Algorithms and Parallel VLSI Architectures 1991: 365-370 |
| 3 | | Mirjam Schönfeld,
Markus Schwiegershausen,
Peter Pirsch:
Synthesis of Intermediate Memories needed for the Data Supply to Processor Arrays.
VLSI 1991: 297-306 |
| 1984 |
|---|
| 2 | | P. Drews,
Peter Pirsch,
K. Schaper:
Circuit Technique for VLSI Design of a Video Codec.
ICC (1) 1984: 250-255 |
| 1983 |
|---|
| 1 | EE | Peter Pirsch,
Arun N. Netravali:
Transmission of gray level images by multilevel dither techniques.
Computers & Graphics 7(1): 31-44 (1983) |
