| 2007 |
|---|
| 117 | EE | Vincent Binet,
Yvon Savaria,
Michel Meunier,
Yves Gagnon:
Modeling the Substrate Noise Injected by a DC-DC Converter.
ISCAS 2007: 309-312 |
| 116 | EE | R. Chebli,
Mohamad Sawan,
Yvon Savaria,
Kamal El-Sankary:
High-Voltage DMOS Integrated Circuits with Floating Gate Protection Technique.
ISCAS 2007: 3343-3346 |
| 115 | EE | Syed Rafay Hasan,
Yvon Savaria:
Crosstalk Effects in Event-Driven Self-Timed Circuits Designed With 90nm CMOS Technology.
ISCAS 2007: 629-632 |
| 114 | EE | Bill Pontikakis,
Hung Tien Bui,
François R. Boyer,
Yvon Savaria:
A Low-Complexity High-Speed Clock Generator for Dynamic Frequency Scaling of FPGA and Standard-Cell Based Designs.
ISCAS 2007: 633-636 |
| 113 | EE | Rahul Singh,
Yves Audet,
Yves Gagnon,
Yvon Savaria:
Integrated Circuit Trimming Technique for Offset Reduction in a Precision CMOS Amplifier.
ISCAS 2007: 709-712 |
| 112 | EE | N. Gorse,
P. Bélanger,
Alexandre Chureau,
El Mostapha Aboulhamid,
Yvon Savaria:
A high-level requirements engineering methodology for electronic system-level design.
Computers & Electrical Engineering 33(4): 249-268 (2007) |
| 111 | EE | Mame Maria Mbaye,
Normand Bélanger,
Yvon Savaria,
Samuel Pierre:
A Novel Application-specific Instruction-set Processor Design Approach for Video Processing Acceleration.
VLSI Signal Processing 47(3): 297-315 (2007) |
| 2006 |
|---|
| 110 | EE | Hung Tien Bui,
Yvon Savaria:
High speed differential pulse-width control loop based on frequency-to-voltage converters.
ACM Great Lakes Symposium on VLSI 2006: 53-56 |
| 109 | EE | Ali Naderi,
Mohamad Sawan,
Yvon Savaria:
Design of an Active-RC Bandpass Filter for a Subsampling RF Delta Modulator.
CCECE 2006: 967-970 |
| 108 | EE | N. Ignat,
B. Nicolescu,
Yvon Savaria,
Gabriela Nicolescu:
Soft-error classification and impact analysis on real-time operating systems.
DATE 2006: 182-187 |
| 107 | EE | Abdelaziz Ammari,
Régis Leveugle,
B. Nicolescu,
Yvon Savaria:
Evaluation of a Software-Based Error Detection Technique by RT-Level Fault Injection.
DELTA 2006: 488-493 |
| 106 | EE | Bill Pontikakis,
François R. Boyer,
Yvon Savaria:
A 0.8V algorithmically defined buffer and ring oscillator low-energy design for nanometer SoCs.
ISCAS 2006 |
| 105 | EE | Ali Naderi,
Mohamad Sawan,
Yvon Savaria:
A novel 2-GHz band-pass delta modulator dedicated to wireless receivers.
ISCAS 2006 |
| 104 | EE | S. Hashemi,
Mohamad Sawan,
Yvon Savaria:
A power planning model for implantable stimulators.
ISCAS 2006 |
| 103 | EE | Ami Castonguay,
Yvon Savaria:
Architecture of a hypertransport tunnel.
ISCAS 2006 |
| 102 | EE | M. Mbaye,
D. Lebel,
Normand Bélanger,
Yvon Savaria,
Samuel Pierre:
Design exploration with an application-specific instruction-set processor for ELA deinterlacing.
ISCAS 2006 |
| 101 | EE | Z. Huang,
Yvon Savaria,
Mohamad Sawan,
R. Meinga:
High-voltage operational amplifier based on dual floating-gate transistors.
ISCAS 2006 |
| 100 | EE | Houman Zarrabi,
Haydar Saaied,
Asim J. Al-Khalili,
Yvon Savaria:
Zero skew differential clock distribution network.
ISCAS 2006 |
| 99 | EE | Marc-André Cantin,
Yvon Savaria,
D. Prodanos,
Pierre Lavoie:
A Metric for Automatic Word-Length Determination of Hardware Datapaths.
IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2228-2231 (2006) |
| 2005 |
|---|
| 98 | EE | Alexandre Chureau,
Yvon Savaria,
El Mostapha Aboulhamid:
The Role of Model-Level Transactors and UML in Functional Prototyping of Systems-on-Chip: A Software-Radio Application.
DATE 2005: 698-703 |
| 97 | EE | Ami Castonguay,
Yvon Savaria:
A HyperTransport Chip-to-Chip Interconnect Tunnel Developed Using SystemC.
IEEE International Workshop on Rapid System Prototyping 2005: 264-266 |
| 96 | EE | D. Marche,
Yves Gagnon,
Yvon Savaria:
. A new switch compensation technique for inverted R-2R ladder DACs.
ISCAS (1) 2005: 196-199 |
| 95 | EE | H. G. Epassa,
François R. Boyer,
Yvon Savaria:
Implementation of a cycle by cycle variable speed processor.
ISCAS (4) 2005: 3335-3338 |
| 94 | EE | A. Landry,
Mohamed Nekili,
Yvon Savaria:
A novel 2 GHz multi-layer AMBA high-speed bus interconnect matrix for SoC platforms.
ISCAS (4) 2005: 3343-3346 |
| 93 | EE | S. Catudal,
Marc-André Cantin,
Yvon Savaria:
Parameters estimation applied to automatic video processing algorithms validation.
ISCAS (4) 2005: 3439-3442 |
| 92 | EE | M. Mbaye,
Normand Bélanger,
Yvon Savaria,
Samuel Pierre:
Application specific instruction-set processor generation for video processing based on loop optimization.
ISCAS (4) 2005: 3515-3518 |
| 91 | EE | G. Wild,
Yvon Savaria,
Michel Meunier:
Characterization of laser-induced photoexcitation effect on a surrounding CMOS ring oscillator.
ISCAS (4) 2005: 3696-3699 |
| 90 | EE | G. Provost,
Marc-André Cantin,
Mohamad Sawan,
Christian Cardinal,
Yvon Savaria,
David Haccoun:
Fast parameters optimization of an iterative decoder using a configurable hardware accelerator.
ISCAS (4) 2005: 4159-4162 |
| 89 | EE | Simon Rioux,
Alain Lacourse,
Yvon Savaria,
Michel Meunier:
Design methods for CMOS low-current finely tunable voltage references covering a wide output range.
ISCAS (5) 2005: 4257-4260 |
| 88 | EE | Max-Elie Salomon,
Abdelhakim Khouas,
Yvon Savaria:
A complete spurs distribution model for direct digital period synthesizers.
ISCAS (5) 2005: 4859-4862 |
| 87 | EE | Dinh Hung Dang,
Yvon Savaria,
Mohamad Sawan:
A novel approach for implementing ultra-high speed flash ADC using MCML circuits.
ISCAS (6) 2005: 6158-6161 |
| 86 | EE | Wei Ling,
Yvon Savaria:
Analysis of Wave-Pipelined Domino Logic Circuit and Clocking Styles Subject to Parametric Variations.
ISQED 2005: 688-693 |
| 85 | EE | Robert Grou-Szabo,
Hany Ghattas,
Yvon Savaria,
Gabriela Nicolescu:
Component-Based Methodology for Hardware Design of a Dataflow Processing Network.
IWSOC 2005: 289-294 |
| 84 | EE | Bill Pontikakis,
François R. Boyer,
Yvon Savaria:
Performance Improvement of Configurable Processor Architectures Using a Variable Clock Period.
IWSOC 2005: 454-458 |
| 83 | EE | Hung Tien Bui,
Yvon Savaria:
A Generic Method for Embedded Measurement and Compensation of Process and Temperature Variations in SoCs.
IWSOC 2005: 557-562 |
| 82 | EE | Noureddine Chabini,
El Mostapha Aboulhamid,
Ismaïl Chabini,
Yvon Savaria:
Scheduling and optimal register placement for synchronous circuits derived using software pipelining techniques.
ACM Trans. Design Autom. Electr. Syst. 10(2): 187-204 (2005) |
| 81 | EE | Hakim Khali,
Yvon Savaria,
Jean-Louis Houle:
A system level implementation strategy and partitioning heuristic for LUT-based applications.
Computers & Electrical Engineering 31(7): 485-502 (2005) |
| 2004 |
|---|
| 80 | EE | Olivier Duval,
L.-P. Lafrance,
Yvon Savaria,
Pierre Desjardins:
An Integrated Test Platform for Nanostructure Electrical Characterization.
ICMENS 2004: 237-242 |
| 79 | EE | Mohammed Layachi,
Yvon Savaria,
Alain Rochefort:
The Effect of p-Coupling on the Electronic Properties of 1, 4-Dithiol Benzene Stacking.
ICMENS 2004: 588-592 |
| 78 | EE | B. Nicolescu,
Yvon Savaria,
Raoul Velazco:
Performance Evaluation and Failure Rate Prediction for the Soft Implemented Error Detection Technique.
IOLTS 2004: 233-238 |
| 77 | | Kevin Peterson,
Yvon Savaria:
Assertion-based on-line verification and debug environment for complex hardware systems.
ISCAS (2) 2004: 685-688 |
| 76 | EE | Badre Izouggaghen,
Abdelhakim Khouas,
Yvon Savaria:
Spurs modeling in direct digital period synthesizers related to phase accumulator truncation.
ISCAS (3) 2004: 389-392 |
| 75 | | Olivier Duval,
Yvon Savaria:
An on-chip delay measurements module for nanostructures characterization.
ISCAS (3) 2004: 721-724 |
| 74 | | Hung Tien Bui,
Yvon Savaria:
Shunt-peaking in MCML gates and its application in the design of a 20 Gb/s half-rate phase detector.
ISCAS (4) 2004: 369-372 |
| 73 | | Dorin Emil Calbaza,
Ioan Cordos,
Nigel Seth-Smith,
Yvon Savaria:
An ADPLL circuit using a DDPS for genlock applications.
ISCAS (4) 2004: 569-572 |
| 72 | EE | D. Morin,
F. Normandin,
M.-E. Grandmaison,
H. Dang,
Yvon Savaria,
Mohamad Sawan:
An Intellectual Property Module for Auto-Calibration of Time-Interleaved Pipelined Analog-to-Digital Converters.
IWSOC 2004: 111-114 |
| 71 | EE | Hung Tien Bui,
Yvon Savaria:
10 GHz PLL Using Active Shunt-Peaked MCML Gates and Improved Frequency Acquisition XOR Phase Detector in 0.18 µm CMOS.
IWSOC 2004: 115-118 |
| 70 | EE | Pascal Nsame,
Yvon Savaria:
A Customizable Embedded SoC Platform Architecture.
IWSOC 2004: 299-304 |
| 69 | EE | Alexandre Chureau,
Yvon Savaria,
El Mostapha Aboulhamid:
Interface-based Design of Systems-on-Chip using UML-RT.
IWSOC 2004: 39-44 |
| 68 | EE | L.-P. Lafrance,
Yvon Savaria:
A Framework for Implementing Reusable Digital Signal Processing Modules.
IWSOC 2004: 51-54 |
| 67 | EE | S. Regimbal,
Yvon Savaria,
Guy Bois:
Verification Strategy Determination Using Dependence Analysis of Transaction-Level Models.
IWSOC 2004: 87-92 |
| 66 | EE | Marc-André Cantin,
S. Regimbal,
S. Catudal,
Yvon Savaria:
A Unified Environment to Assess Image Quality in Video Processing.
Journal of Circuits, Systems, and Computers 13(6): 1289-1306 (2004) |
| 2003 |
|---|
| 65 | EE | Noureddine Chabini,
Ismaïl Chabini,
El Mostapha Aboulhamid,
Yvon Savaria:
Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs.
ACM Great Lakes Symposium on VLSI 2003: 221-224 |
| 64 | EE | Meng Lu,
Yvon Savaria,
Bing Qiu,
Jacques Taillefer:
IEEE 1149.1 Based Defect and Fault Tolerant Scan Chain for Wafer Scale Integration.
DFT 2003: 18-25 |
| 63 | EE | B. Nicolescu,
P. Peronnard,
Raoul Velazco,
Yvon Savaria:
Efficiency of Transient Bit-Flips Detection by Software Means: A Complete Study.
DFT 2003: 377-384 |
| 62 | EE | B. Nicolescu,
Yvon Savaria,
Raoul Velazco:
SIED: Software Implemented Error Detection.
DFT 2003: 589-596 |
| 61 | EE | Mathieu Renaud,
Yvon Savaria:
A CMOS three-state frequency detector complementary to an enhanced linear phase detector for PLL, DLL or high frequency clock skew measurement.
ISCAS (3) 2003: 148-151 |
| 60 | EE | Yiyan Tang,
Lie Qian,
Yuke Wang,
Yvon Savaria:
A new memory reference reduction method for FFT implementation on DSP.
ISCAS (4) 2003: 496-499 |
| 59 | EE | S. Regimbal,
Jean-Francois Lemire,
Yvon Savaria,
Guy Bois,
El Mostapha Aboulhamid,
A. Baron:
Automating Functional Coverage Analysis Based on an Executable Specification.
IWSOC 2003: 228-234 |
| 58 | EE | Eric Granger,
Yvon Savaria,
Pierre Lavoie:
A Pattern Reordering Approach Based on Ambiguity Detection for Online Category Learning.
IEEE Trans. Pattern Anal. Mach. Intell. 25(4): 524-528 (2003) |
| 57 | EE | Noureddine Chabini,
Ismaïl Chabini,
El Mostapha Aboulhamid,
Yvon Savaria:
Methods for minimizing dynamic power consumption in synchronous designs with multiple supply voltages.
IEEE Trans. on CAD of Integrated Circuits and Systems 22(3): 346-351 (2003) |
| 2002 |
|---|
| 56 | EE | Bing Qiu,
Yvon Savaria,
Meng Lu,
Chunyan Wang,
Claude Thibeault:
Yield Modeling of a WSI Telecom Router Architecture.
DFT 2002: 314-324 |
| 55 | EE | J. Dido,
N. Geraudie,
L. Loiseau,
O. Payeur,
Yvon Savaria,
D. Poirier:
A flexible floating-point format for optimizing data-paths and operators in FPGA based DSPs.
FPGA 2002: 50-55 |
| 54 | EE | Y. Fouzar,
Yvon Savaria,
Mohamad Sawan:
A CMOS phase-locked loop with an auto-calibrated VCO.
ISCAS (3) 2002: 177-180 |
| 53 | EE | A. Bendali,
Yvon Savaria:
Low-voltage bandgap reference with temperature compensation based on a threshold voltage technique.
ISCAS (3) 2002: 201-204 |
| 52 | EE | Mathieu Renaud,
Yvon Savaria:
A linear phase detector for arbitrary clock signals.
ISCAS (4) 2002: 775-778 |
| 51 | EE | L.-P. Lafrance,
Marc-André Cantin,
Yvon Savaria,
S. H. Sung,
Pierre Lavoie:
Architecture and performance characterization of hardware and software implementations of the Crozier frequency estimation algorithm.
ISCAS (4) 2002: 823-826 |
| 50 | EE | Hakim Khali,
Yvon Savaria:
FPGA Implementation of a Sub-pixel Correction Algorithm for Active Laser Range Finders.
MVA 2002: 604-606 |
| 49 | EE | Zhong-Fang Jin,
J.-J. Laurin,
Yvon Savaria:
A practical approach to model long MIS interconnects in VLSI circuits.
IEEE Trans. VLSI Syst. 10(4): 494-507 (2002) |
| 2001 |
|---|
| 48 | | Noureddine Chabini,
El Mostapha Aboulhamid,
Yvon Savaria:
Determining Schedules for Reducing Power Consumption Using Multiple Supply Voltages.
ICCD 2001: 546-552 |
| 47 | EE | Mohamed Nekili,
Yvon Savaria,
Guy Bois:
Minimizing process-induced skew using delay tuning.
ISCAS (4) 2001: 426-429 |
| 46 | EE | Y. Fouzar,
Yvon Savaria,
Mohamad Sawan:
A new controlled gain phase-locked loop technique.
ISCAS (4) 2001: 810-813 |
| 45 | EE | L. Theriault,
D. Auder,
Yvon Savaria:
Performance estimators for hardware/software co-design.
ISCAS (5) 2001: 17-20 |
| 44 | EE | Marc-André Cantin,
Yvon Savaria,
D. Prodanos,
Pierre Lavoie:
An automatic word length determination method.
ISCAS (5) 2001: 53-56 |
| 43 | | Noureddine Chabini,
Yvon Savaria:
Methods for optimizing register placement in synchronous circuits derived using software pipelining techniques.
ISSS 2001: 209-214 |
| 42 | EE | Ginette Monté,
Bernard Antaki,
Serge Patenaude,
Yvon Savaria,
Claude Thibeault,
Pieter M. Trouborst:
Tools for the Characterization of Bipolar CML Testability.
VTS 2001: 388-395 |
| 41 | EE | François R. Boyer,
El Mostapha Aboulhamid,
Yvon Savaria,
Michel Boyer:
Optimal design of synchronous circuits using software pipelining techniques.
ACM Trans. Design Autom. Electr. Syst. 6(4): 516-532 (2001) |
| 2000 |
|---|
| 40 | EE | Olivier Hébert,
Ivan C. Kraljic,
Yvon Savaria:
A method to derive application-specific embedded processing cores.
CODES 2000: 88-92 |
| 1999 |
|---|
| 39 | EE | Bernard Antaki,
Yvon Savaria,
Nanhan Xiong,
Saman Adham:
Design For Testability Method for CML Digital Circuits.
DATE 1999: 360-367 |
| 38 | EE | Cynthia Cousineau,
François Laperle,
Yvon Savaria:
Design of a JTAG Based Run Time Reconfigurable System.
FCCM 1999: 268-269 |
| 37 | EE | Dorin Emil Calbaza,
Yvon Savaria:
Jitter model of direct digital synthesis clock generators.
ISCAS (1) 1999: 1-4 |
| 36 | EE | B. Le Chapelain,
A. Mechain,
Yvon Savaria,
Guy Bois:
Development of a high performance TSPC library for implementation of large digital building blocks.
ISCAS (1) 1999: 443-446 |
| 35 | EE | Zhong-Fang Jin,
J.-J. Laurin,
Yvon Savaria,
P. Garon:
A new approach to analyze interconnect delays in RC wire models.
ISCAS (6) 1999: 246-249 |
| 34 | EE | B. Bosi,
Guy Bois,
Yvon Savaria:
Reconfigurable pipelined 2-D convolvers for fast digital signal processing.
IEEE Trans. VLSI Syst. 7(3): 299-308 (1999) |
| 33 | EE | Pierre Lavoie,
Jean-Francois Crespo,
Yvon Savaria:
Generalization, discrimination, and multiple categorization using adaptive resonance theory.
IEEE Transactions on Neural Networks 10(4): 757-767 (1999) |
| 1998 |
|---|
| 32 | EE | Daniel Audet,
Steve Masson,
Yvon Savaria:
Reducing Fault Sensitivity of Microprocessor-Based Systems by Modifying Workload Structure.
DFT 1998: 241- |
| 31 | EE | Pascal Poiré,
Marc-André Cantin,
Hervé Daniel,
Yves Blaquière,
Yvon Savaria:
A Comparative Analysis of Fuzzy ART Neural Network Implementations: The Advantages of Reconfigurable Computing.
FCCM 1998: 304-305 |
| 30 | EE | Mohamed Nekili,
Yvon Savaria,
Guy Bois:
Design of Clock Distribution Networks in Presence of Process Variations.
Great Lakes Symposium on VLSI 1998: 95-102 |
| 1997 |
|---|
| 29 | EE | Michel Kafrouni,
Claude Thibeault,
Yvon Savaria:
A Cost Model for VLSI / MCM Systems.
DFT 1997: 148-156 |
| 28 | EE | Yves Gagnon,
Yvon Savaria,
Michel Meunier,
Claude Thibeault:
Are defect-tolerant circuits with redundancy really cost-effective? Complete and realistic cost model.
DFT 1997: 157-165 |
| 27 | EE | Mohamed Nekili,
Guy Bois,
Yvon Savaria:
Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations.
IEEE Trans. VLSI Syst. 5(2): 161-174 (1997) |
| 1996 |
|---|
| 26 | EE | Mohamed Soufi,
Steve Rochon,
Yvon Savaria,
Bozena Kaminska:
Design and performance of CMOS TSPC cells for high speed pseudo random testing.
VTS 1996: 368-373 |
| 25 | | Yervant Zorian,
Tom Anderson,
Yvon Savaria,
Claude Thibeault,
André Ivanov:
Panel Summaries.
IEEE Design & Test of Computers 13(3): 6, 110-112 (1996) |
| 24 | EE | Yves Blaquière,
Michel Dagenais,
Yvon Savaria:
Timing analysis speed-up using a hierarchical and a multimode approach.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(2): 244-255 (1996) |
| 1995 |
|---|
| 23 | EE | Janusz Rzeszut,
Bozena Kaminska,
Yvon Savaria:
A new method for testing mixed analog and digital circuits.
Asian Test Symposium 1995: 127-132 |
| 22 | | Mohamed Soufi,
Yvon Savaria,
Bozena Kaminska:
On Using Partial Reset for Pseudo-Random Testing.
ISCAS 1995: 949-952 |
| 21 | EE | Mohamed Soufi,
Yvon Savaria,
Bozena Kaminska:
On the design of at-speed testable VLSI circuits.
VTS 1995: 290-295 |
| 20 | | Mohamed Soufi,
Yvon Savaria,
F. Darlay,
Bozena Kaminska:
Producing Reliable Initialization and Test of Sequential Circuits with Pseudorandom Vectors.
IEEE Trans. Computers 44(10): 1251-1256 (1995) |
| 19 | | Claude Thibeault,
Yvon Savaria,
Jean-Louis Houle:
Equivalence Proofs of Some Yield Modeling Methods for Defect-Tolerant Integrated Circuits.
IEEE Trans. Computers 44(5): 724-728 (1995) |
| 1994 |
|---|
| 18 | | Rachid Kermouche,
Yvon Savaria:
Defect and Fault Tolerant Scan Chains.
DFT 1994: 185-193 |
| 17 | | Abdessatar Abderrahman,
Bozena Kaminska,
Yvon Savaria:
Estimation of Simultaneous Switching Power and Ground Noise of Static CMOS Combinational Circuits.
EDAC-ETC-EUROASIC 1994: 658 |
| 16 | | Jean-Francois Crespo,
Pierre Lavoie,
Yvon Savaria:
Fast Convergence with Low Precision Weights in ART1 Networks.
ISCAS 1994: 237-240 |
| 15 | | Mohamed Nekili,
Yvon Savaria,
Guy Bois:
A Fast Low-Power Driver for Long Interconnections in VLSI Systems.
ISCAS 1994: 343-346 |
| 14 | | Sameh Ghannoum,
Dmitri Chtchvyrkov,
Yvon Savaria:
A Comparative Study of Single-Phase Clocked Latches Using Estimation Criteria.
ISCAS 1994: 347-350 |
| 13 | | Yvon Savaria,
Dmitri Chtchvyrkov,
John F. Currie:
A Fast CMOS Voltage-Controlled Ring Oscillator.
ISCAS 1994: 359-362 |
| 12 | | Naim Ben Hamida,
Bozena Kaminska,
Yvon Savaria:
Pseudo-Random Vector Compaction for Sequential Testability.
ISCAS 1994: 63-66 |
| 11 | | Claude Thibeault,
Yvon Savaria,
Jean-Louis Houle:
A Fast Method to Evaluate the Optimum Number of Spares in Defect-Tolerant Integrated Circuits.
IEEE Trans. Computers 43(6): 687-698 (1994) |
| 10 | EE | Daniel Audet,
Yvon Savaria,
N. Arel:
Pipelining communications in large VLSI/ULSI systems.
IEEE Trans. VLSI Syst. 2(1): 1-10 (1994) |
| 1993 |
|---|
| 9 | | Fabrizio Lombardi,
Mariagiovanna Sami,
Yvon Savaria,
Renato Stefanelli:
The IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, October 27-29, 1993, Venice, Italy, Proceedings
IEEE Computer Society 1993 |
| 8 | | J. Crépeau,
Claude Thibeault,
Yvon Savaria:
Some Results on Yield and Local Design Rule Relaxation.
DFT 1993: 144-151 |
| 7 | | Naim Ben Hamida,
Bozena Kaminska,
Yvon Savaria:
Initiability: A Measure of Sequential Testability.
ISCAS 1993: 1619-1622 |
| 6 | | Hakim Khali,
Jean-Louis Houle,
Yvon Savaria:
A High Speed Parallel Structure for the Basic Wavelet Transform Algorithm.
ISCAS 1993: 1971-1974 |
| 5 | | Mohamed Nekili,
Yvon Savaria:
Parallel Regeneration of Interconnections in VLSI & ULSI Circuits.
ISCAS 1993: 2023-2026 |
| 1992 |
|---|
| 4 | | Daniel Audet,
Yvon Savaria,
Jean-Louis Houle:
Performance improvements to VLSI parallel systems, using dynamic concatenation of processing resources.
Parallel Computing 18(2): 149-167 (1992) |
| 1989 |
|---|
| 3 | | Yvon Savaria,
Bruno Laguë,
Bozena Kaminska:
A Pragmatic Approach to the Design of Self-Testing Circuits.
ITC 1989: 745-754 |
| 2 | | Bozena Kaminska,
Yvon Savaria:
Design-for-Testability Using Test Design Yield and Decision Theory.
ITC 1989: 884-892 |
| 1984 |
|---|
| 1 | | Yvon Savaria,
Vinod K. Agarwal,
Nicholas C. Rumin,
Jeremiah F. Hayes:
A Design for Machines with Built-In Tolerance to Soft Errors.
ITC 1984: 649-659 |
