ACM Transactions on Architecture and Code Optimization (TACO), Volume 3

Volume 3, Number 1, March 2006

• Brad Calder, Dean M. Tullsen:
  Introduction. 1-2
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• Lin Tan, Brett Brotherton, Timothy Sherwood:
  Bit-split string-matching engines for intrusion detection and prevention. 3-34
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• Priya Nagpurkar, Hussam Mousa, Chandra Krintz, Timothy Sherwood:
  Efficient remote profiling for resource-constrained devices. 35-66
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• Jin Lin, Wei-Chung Hsu, Pen-Chung Yew, Roy Dz-Ching Ju, Tin-Fook Ngai:
  Recovery code generation for general speculative optimizations. 67-89
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• Yoonseo Choi, Hwansoo Han:
  Optimal register reassignment for register stack overflow minimization. 90-114
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Volume 3, Number 2, June 2006

• Jingling Xue, Qiong Cai:
  A lifetime optimal algorithm for speculative PRE. 115-155
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• Joseph J. Sharkey, Dmitry V. Ponomarev, Kanad Ghose, Oguz Ergin:
  Instruction packing: Toward fast and energy-efficient instruction scheduling. 156-181
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• Luis Ceze, Karin Strauss, James Tuck, Josep Torrellas, Jose Renau:
  CAVA: Using checkpoint-assisted value prediction to hide L2 misses. 182-208
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• Lixin Zhang, Michael Parker, John B. Carter:
  Efficient address remapping in distributed shared-memory systems. 209-229
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Volume 3, Number 3, September 2006

• Min Zhao, Bruce R. Childers, Mary Lou Soffa:
  An approach toward profit-driven optimization. 231-262
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• Kim M. Hazelwood, Michael D. Smith:
  Managing bounded code caches in dynamic binary optimization systems. 263-294
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• Olivier Rochecouste, Gilles Pokam, André Seznec:
  A case for a complexity-effective, width-partitioned microarchitecture. 295-326
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• Ahmad Zmily, Christos Kozyrakis:
  Block-aware instruction set architecture. 327-357
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Volume 3, Number 4, December 2006

• Jedidiah R. Crandall, Shyhtsun Felix Wu, Frederic T. Chong:
  Minos: Architectural support for protecting control data. 359-389
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• Jaydeep Marathe, Frank Mueller, Bronis R. de Supinski:
  Analysis of cache-coherence bottlenecks with hybrid hardware/software techniques. 390-423
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• Ilya Ganusov, Martin Burtscher:
  Future execution: A prefetching mechanism that uses multiple cores to speed up single threads. 424-449
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• Michele Co, Dee A. B. Weikle, Kevin Skadron:
  Evaluating trace cache energy efficiency. 450-476
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• Shiwen Hu, Madhavi Gopal Valluri, Lizy Kurian John:
  Effective management of multiple configurable units using dynamic optimization. 477-501
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• Chris Bentley, Scott A. Watterson, David K. Lowenthal, Barry Rountree:
  Implicit array bounds checking on 64-bit architectures. 502-527
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