PACT 2001: Barcelona, Catalunya, Spain

Keynote Address

Session 1: Simulation and Modeling

• Timothy Sherwood, Erez Perelman, Brad Calder:
  Basic Block Distribution Analysis to Find Periodic Behavior and Simulation Points in Applications. 3-14
  
• Sébastien Nussbaum, James E. Smith:
  Modeling Superscalar Processors via Statistical Simulation. 15-24
  
• Lieven Eeckhout, Koenraad De Bosschere:
  Hybrid Analytical-Statistical Modeling for Efficiently Exploring Architecture and Workload Design Spaces. 25-34
  

Session 2: Efficient Caches

• Roni Rosner, Avi Mendelson, Ronny Ronen:
  Filtering Techniques to Improve Trace-Cache Efficiency. 37-48
  
• Brannon Batson, T. N. Vijaykumar:
  Reactive-Associative Caches. 49-60
  
• Huiyang Zhou, Mark C. Toburen, Eric Rotenberg, Thomas M. Conte:
  Adaptive Mode Control: A Static-Power-Efficient Cache Design. 61-70
  

Session 3: Specialized Instruction Sets

• Ben H. H. Juurlink, Stamatis Vassiliadis, Dmitri Tcheressiz, Harry A. G. Wijshoff:
  Implementation and Evaluation of the Complex Streamed Instruction Set. 73-82
  
• Jesús Corbal, Roger Espasa, Mateo Valero:
  On the Efficiency of Reductions in µ-SIMD Media Extensions. 83-94
  

Keynote Address

Session 4: Prediction and Recovery

• Daniel A. Jiménez, Heather L. Hanson, Calvin Lin:
  Boolean Formula-Based Branch Prediction for Future Technologies. 97-106
  
• Renju Thomas, Manoj Franklin:
  Using Dataflow Based Context for Accurate Value Prediction. 107-117
  
• Enric Morancho, José María Llabería, Àngel Olivé:
  Recovery Mechanism for Latency Misprediction. 118-128
  

Session 5: Memory Optimization

• Bharat Chandramouli, John B. Carter, Wilson C. Hsieh, Sally A. McKee:
  A Cost Framework for Evaluating Integrated Restructuring Optimizations. 131-140
  
• Xianglong Huang, Zhenlin Wang, Kathryn S. McKinley:
  Compiling for the Impulse Memory Controller. 141-150
  
• Trishul M. Chilimbi:
  On the Stability of Temporal Data Reference Profiles. 151-160
  

Session 6: Program Optimization

• Erik M. Nystrom, Ronald D. Barnes, Matthew C. Merten, Wen-mei W. Hwu:
  Code Reordering and Speculation Support for Dynamic Optimization System. 163-174
  
• Josep M. Codina, F. Jesús Sánchez, Antonio González:
  A Unified Modulo Scheduling and Register Allocation Technique for Clustered Processors. 175-184
  
• Michael Penner, Viktor K. Prasanna:
  Cache-Friendly Implementations of Transitive Closure. 185-196
  

Session 7: Technology Implications

• Jaehyuk Huh, Doug Burger, Stephen W. Keckler:
  Exploring the Design Space of Future CMPs. 199-210
  
• James Burns, Jean-Luc Gaudiot:
  Area and System Clock Effects on SMT/CMP Processors. 211-218
  

Keynote Address

Session 8: Parallel Machines

• Fredrik Warg, Per Stenström:
  Limits on Speculative Module-Level Parallelism in Imperative and Object-Oriented Programs on CMP Platforms. 221-230
  
• Renato Ferreira, Joel H. Saltz, Gagan Agrawal:
  Compiler and Runtime Analysis for Efficient Communication in Data Intensive Applications. 231-242
  
• María Jesús Garzarán, Milos Prvulovic, Ye Zhang, Josep Torrellas, Alin Jula, Hao Yu, Lawrence Rauchwerger:
  Architectural Support for Parallel Reductions in Scalable Shared-Memory Multiprocessors. 243-254
  

Session 9: Data Prefetching

• Gautam Doshi, Rakesh Krishnaiyer, Kalyan Muthukumar:
  Optimizing Software Data Prefetches with Rotating Registers. 257-267
  
• Nicholas Kohout, Seungryul Choi, Dongkeun Kim, Donald Yeung:
  Multi-Chain Prefetching: Effective Exploitation of Inter-Chain Memory Parallelism for Pointer-Chasing Codes. 268-279
  
• Brendon Cahoon, Kathryn S. McKinley:
  Data Flow Analysis for Software Prefetching Linked Data Structures in Java. 280-291
  
• Vijay S. Pai, Sarita V. Adve:
  Comparing and Combining Read Miss Clustering and Software Prefetching. 292-303
  

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