PACT 2008: Toronto, Ontario, Canada

• Norm Rubin:
  GPU evolution: will graphics morph into compute? 1
  

Compilation

• Dorit Nuzman, Ayal Zaks:
  Outer-loop vectorization: revisited for short SIMD architectures. 2-11
  
• Keith D. Cooper, Jason Eckhardt, Ken Kennedy:
  Redundancy elimination revisited. 12-21
  
• Xuejun Yang, Ying Zhang, Jingling Xue, Ian Rogers, Gen Li, Guibin Wang:
  Exploiting loop-dependent stream reuse for stream processors. 22-31
  
• Katherine E. Coons, Behnam Robatmili, Matthew E. Taylor, Bertrand A. Maher, Doug Burger, Kathryn S. McKinley:
  Feature selection and policy optimization for distributed instruction placement using reinforcement learning. 32-42
  

CMP architecture design

• Bogdan F. Romanescu, Daniel J. Sorin:
  Core cannibalization architecture: improving lifetime chip performance for multicore processors in the presence of hard faults. 43-51
  
• Henry Wong, Anne Bracy, Ethan Schuchman, Tor M. Aamodt, Jamison D. Collins, Perry H. Wang, Gautham N. Chinya, Ankur Khandelwal Groen, Hong Jiang, Hong Wang:
  Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor. 52-61
  
• Gordon B. Bell, Mikko H. Lipasti:
  Skewed redundancy. 62-71
  

Analyzing applications

• Christian Bienia, Sanjeev Kumar, Jaswinder Pal Singh, Kai Li:
  The PARSEC benchmark suite: characterization and architectural implications. 72-81
  
• Graham D. Price, John Giacomoni, Manish Vachharajani:
  Visualizing potential parallelism in sequential programs. 82-90
  
• Fang Liu, Fei Guo, Yan Solihin, Seongbeom Kim, Abdulaziz Eker:
  Characterizing and modeling the behavior of context switch misses. 91-101
  

I/O optimizations

• Hiroshige Hayashizaki, Yutaka Sugawara, Mary Inaba, Kei Hiraki:
  MCAMP: communication optimization on massively parallel machines with hierarchical scratch-pad memory. 102-111
  
• Seung Woo Son, Sai Prashanth Muralidhara, Ozcan Ozturk, Mahmut T. Kandemir, Ibrahim Kolcu, Mustafa Karaköy:
  Profiler and compiler assisted adaptive I/O prefetching for shared storage caches. 112-121
  
• Costin Iancu, Steven A. Hofmeyr:
  Runtime optimization of vector operations on large scale SMP clusters. 122-132
  
• Saman P. Amarasinghe:
  (How) can programmers conquer the multicore menace? 133
  

Multicore memory hierarchy design (part 1)

• Enric Herrero, José González, Ramon Canal:
  Distributed cooperative caching. 134-143
  
• Seth H. Pugsley, Manu Awasthi, Niti Madan, Naveen Muralimanohar, Rajeev Balasubramonian:
  Scalable and reliable communication for hardware transactional memory. 144-154
  
• Hemayet Hossain, Sandhya Dwarkadas, Michael C. Huang:
  Improving support for locality and fine-grain sharing in chip multiprocessors. 155-165
  

Reconfigurable architecture optimization

• Hyunchul Park, Kevin Fan, Scott A. Mahlke, Taewook Oh, Heeseok Kim, Hong-seok Kim:
  Edge-centric modulo scheduling for coarse-grained reconfigurable architectures. 166-176
  
• Ke Meng, Russ Joseph, Robert P. Dick, Li Shang:
  Multi-optimization power management for chip multiprocessors. 177-186
  
• Divya Gulati, Changkyu Kim, Simha Sethumadhavan, Stephen W. Keckler, Doug Burger:
  Multitasking workload scheduling on flexible-core chip multiprocessors. 187-196
  

Multicore memory hierarchy design (part 2)

• Noel Eisley, Li-Shiuan Peh, Li Shang:
  Leveraging on-chip networks for data cache migration in chip multiprocessors. 197-207
  
• Aamer Jaleel, William Hasenplaugh, Moinuddin K. Qureshi, Julien Sebot, Simon C. Steely Jr., Joel S. Emer:
  Adaptive insertion policies for managing shared caches. 208-219
  
• Yunlian Jiang, Xipeng Shen, Jie Chen, Rahul Tripathi:
  Analysis and approximation of optimal co-scheduling on chip multiprocessors. 220-229
  

Multithreading improvements

• Huaping Wang, Israel Koren, C. Mani Krishna:
  An adaptive resource partitioning algorithm for SMT processors. 230-239
  
• Qiong Cai, José González, Ryan Rakvic, Grigorios Magklis, Pedro Chaparro, Antonio González:
  Meeting points: using thread criticality to adapt multicore hardware to parallel regions. 240-249
  

Middleware and runtime systems

• Matthew Curtis-Maury, Ankur Shah, Filip Blagojevic, Dimitrios S. Nikolopoulos, Bronis R. de Supinski, Martin Schulz:
  Prediction models for multi-dimensional power-performance optimization on many cores. 250-259
  
• Bingsheng He, Wenbin Fang, Qiong Luo, Naga K. Govindaraju, Tuyong Wang:
  Mars: a MapReduce framework on graphics processors. 260-269
  
• Tibor Horvath, Kevin Skadron:
  Multi-mode energy management for multi-tier server clusters. 270-279
  

Programming the memory hierarchy

• Manman Ren, Ji Young Park, Mike Houston, Alex Aiken, William J. Dally:
  A tuning framework for software-managed memory hierarchies. 280-291
  
• Marc González, Nikola Vujic, Xavier Martorell, Eduard Ayguadé, Alexandre E. Eichenberger, Tong Chen, Zehra Sura, Tao Zhang, Kevin O'Brien, Kathryn M. O'Brien:
  Hybrid access-specific software cache techniques for the cell BE architecture. 292-302
  
• Jaejin Lee, Sangmin Seo, Chihun Kim, Junghyun Kim, Posung Chun, Zehra Sura, Jungwon Kim, Sangyong Han:
  COMIC: a coherent shared memory interface for cell be. 303-314
  

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