1. ACSD 1998: Fukushima, Japan

@proceedings{DBLP:conf/acsd/1998,
  title     = {1st International Conference on Application of Concurrency to
               System Design (ACSD '98), 23-26 March 1998, Fukushima, Japan},
  booktitle = {ACSD},
  publisher = {IEEE Computer Society},
  year      = {1998},
  isbn      = {0-8186-8350-3},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

Tutorial Papers

• Jordi Cortadella:
  Combining Structural and Symbolic Methods for the Verification of Concurrent Systems. 2-7
  
• Jainendra Kumar, Carl Pixley:
  Logic and Functional Verification in a Commercial Semiconductor Environment. 8-15
  
• Naoshi Uchihira:
  How to Make Concurrent Programs Highly Reliable- More than State Space Analysis. 16-23
  
• Luciano Lavagno:
  System-Level Design Models and Implementation Techniques. 24-
  

Hierarchical Models

• Bilung Lee, Edward A. Lee:
  Hierarchical Concurrent Finite State Machines in Ptolemy. 34-40
  
• Radu Grosu, Gheorghe Stefanescu, Manfred Broy:
  Visual Formalisms Revisited. 41-51
  
• Jean-René Beauvais, Roland Houdebine, Paul Le Guernic, Éric Rutten, Thierry Gautier:
  A Translation of Statecharts into Signal Approach of Time, Interoperability. 52-
  

Hierarchical Verification

• Tomohiro Yoneda, Yutaka Ohtsuka, Märt Saarepera:
  Verification of Parameterized Asynchronous Circuits: A Case Study. 64-74
  
• Antti Valmari, Ilkka Kokkarinen:
  Unbounded Verification Results by Finite-State Compositional Techniques: 10^any States and Beyond. 75-
  

Systems with Timing

• Dang Van Hung:
  Modeling and Verification of Biphase Mark Protocolsin Duration Calculus Using PVS. 88-98
  
• Kazuhiro Nakamura, Satoshi Yamane:
  Formal Verification of Real-Time Software by Symbolic Model-Checker. 99-108
  
• Antonio Cerone, David A. Kearney, George J. Milne:
  Integrating the Verification of Timing, Performance and Correctness Properties of Concurrent Systems. 109-119
  
• Michael V. Goncharov, Alexander B. Smirnov, Nikolai Starodoubtsev, Ilya V. Klotchkov:
  Timing Extensions of STG Model and a Method to Simulate Timed STG Behavior in VHDL Environment. 120-
  

PN-Based Verification

• Krzysztof Bilinski, Erik L. Dagless:
  Efficient Approach to Symbolic State Exploration of Complex Parallel Controllers. 132-142
  
• Toshiyuki Miyamoto, Sadatoshi Kumagai:
  Calculating Place Capacity for Petri Nets Using Unfoldings. 143-151
  
• Alex Kondratyev, Jordi Cortadella, Michael Kishinevsky, Luciano Lavagno, Alexander Taubin, Alexandre Yakovlev:
  Identifying State Coding Conflicts in Asynchronous System Specifications Using Petri Net Unfoldings. 152-
  

High-Level Nets

• Giovanna Di Marzo Serugendo, Nicolas Guelfi:
  Using Object-Oriented Algebraic Nets for the Reverse Engineering of Java Programs: A Case Study. 166-176
  
• Jörg Desel, Ekkart Kindler:
  Proving Correctness of Distributed Algorithms Using High-Level Petri Nets - A Case Study. 177-186
  
• Hagen Völzer:
  Verifying Fault Tolerance of Distributed Algorithms Formally - An Example. 187-
  

Hardware Verification

• Miroslav N. Velev, Randal E. Bryant:
  Verification of Pipelined Microprocessors by Correspondence Checking in Symbolic Ternary Simulation. 200-212
  
• Radu Negulescu:
  Event-Driven Verification of Switch-Level Correctness Concerns. 213-
  

Algebraic Models and Languages

• Howard Bowman, Joost-Pieter Katoen:
  A True Concurrency Semantics for ET-LOTOS. 228-238
  
• Raymond R. Devillers, Maciej Koutny:
  Recursive Nets in the Box Algebra. 239-249
  
• Swarup Mohalik, Ramaswamy Ramanujam:
  A Presentation of Regular Languages in the Assumption - Commitment Framework. 250-
  

Case Studies

• Wil M. P. van der Aalst:
  Modeling and Analyzing Interorganizational Workflows. 262-272
  
• Claudio Demartini, Riccardo Sisto:
  A Java-based Formal Development Environment for Factory Communication Systems. 273-281
  
• Franz Huber, Sascha Molterer, Bernhard Schätz, Oscar Slotosch, Alexander Vilbig:
  Traffic Lights - An AutoFocus Case Study. 282-