ARC 2006: Delft, The Netherlands
Koen Bertels, João M. P. Cardoso, Stamatis Vassiliadis (Eds.): Reconfigurable Computing: Architectures and Applications, Second International Workshop, ARC 2006, Delft, The Netherlands, March 1-3, 2006, Revised Selected Papers. Springer 2006 Lecture Notes in Computer Science
Applications
- Andre Guntoro, Peter Zipf, Oliver Soffke, Harald Klingbeil, Martin Kumm, Manfred Glesner: Implementation of Realtime and Highspeed Phase Detector on FPGA. 1-11
- Gerd Van den Branden, Geert Braeckman, Abdellah Touhafi, Erik F. Dirkx: Case Study: Implementation of a Virtual Instrument on a Dynamically Reconfigurable Platform. 12-17
- Rodrigo Piedade, Leonel Sousa: Configurable Embedded Core for Controlling Electro-Mechanical Systems. 18-23
- J. Gonzalez-Gomez, Ivan Gonzalez, Francisco J. Gomez-Arribas, Eduardo I. Boemo: Evaluation of a Locomotion Algorithm for Worm-Like Robots on FPGA-Embedded Processors. 24-29
- Rodrigo Agís, Javier Díaz, Eduardo Ros, Richard R. Carrillo, Eva M. Ortigosa: Event-Driven Simulation Engine for Spiking Neural Networks on a Chip. 36-45
- Eva M. Ortigosa, Antonio Cañas, R. Rodríguez, Javier Díaz, Sonia Mota: Towards an Optimal Implementation of MLP in FPGA. 46-51
Power
- Kris Heyrman, Antonis Papanikolaou, Francky Catthoor, Peter Veelaert, Koen De Bosschere, Wilfried Philips: Energy Consumption for Transport of Control Information on a Segmented Software-Controlled Communication Architecture. 52-58
- Hiren Joshi, S. S. Verma, G. K. Sharma: Quality Driven Dynamic Low Power Reconfiguration of Handhelds. 59-64
- Joong-ho Park, Bang-Hyun Sung, Seok-Yoon Kim: An Efficient Estimation Method of Dynamic Power Dissipation on VLSI Interconnects. 65-74
Image Processing
- Javier Díaz, Eduardo Ros Vidal, Sonia Mota, Rafael Rodríguez-Gómez: Highly Paralellized Architecture for Image Motion Estimation. 75-86
- Niklas Lepistö, Benny Thörnberg, Mattias O'Nils: Design Exploration of a Video Pre-processor for an FPGA Based SoC. 87-92
- Sunil Shukla, Neil W. Bergmann, Jürgen Becker: QUKU: A Fast Run Time Reconfigurable Platform for Image Edge Detection. 93-98
- Kevin Dale, Jeremy W. Sheaffer, Vinu Vijay Kumar, David P. Luebke, Greg Humphreys, Kevin Skadron: Applications of Small-Scale Reconfigurability to Graphics Processors. 99-108
- Vanderlei Bonato, José A. de Holanda, Eduardo Marques: An Embedded Multi-camera System for Simultaneous Localization and Mapping. 109-114
- Vu Manh Tuan, Yohei Hasegawa, Naohiro Katsura, Hideharu Amano: Performance/Cost Trade-Off Evaluation for the DCT Implementation on the Dynamically Reconfigurable Processor. 115-121
- Francisco Fons, Mariano Fons, Enrique Cantó, Mariano López: Trigonometric Computing Embedded in a Dynamically Reconfigurable CORDIC System-on-Chip. 122-127
- Slawomir Cichon, Marek Gorgon, Miroslaw Pac: Handel-C Design Enhancement for FPGA-Based DV Decoder. 128-133
- Alex Ngouanga, Gilles Sassatelli, Lionel Torres, Thierry Gil, André Borin Suarez, Altamiro Amadeu Susin: Run-Time Resources Management on Coarse Grained, Packet-Switching Reconfigurable Architecture: A Case Study Through the APACHES' Platform. 134-145
- Ignacio Bravo, Pedro Jiménez, Manuel Mazo, José Luis Lázaro, Ernesto Martín Gorostiza: Architecture Based on FPGA's for Real-Time Image Processing. 152-157
- Eduardo Ros Vidal, Javier Díaz, Sonia Mota, F. Vargas-Martín, M. D. Peláez-Coca: Real Time Image Processing on a Portable Aid Device for Low Vision Patients. 158-163
- Sonia Mota, Eduardo Ros Vidal, Javier Díaz, Francisco de Toro: General Purpose Real-Time Image Segmentation System. 164-169
Organization and Architecture
- Sara Román Navarro, Julio Septién, Hortensia Mecha, Daniel Mozos: Constant Complexity Management of 2D HW Multitasking in Run-Time Reconfigurable FPGAs. 187-192
- Kwangsup So, Jin-Sang Kim, Won-Kyung Cho, Young Soo Kim, Doug Young Suh: Implementation of Inner Product Architecture for Increased Flexibility in Bitwidths of Input Array. 199-204
- Su-Shin Ang, George A. Constantinides, Peter Y. K. Cheung, Wayne Luk: A Flexible Multi-port Caching Scheme for Reconfigurable Platforms. 205-216
- Nikolaos Vassiliadis, George Theodoridis, Spiridon Nikolaidis: Enhancing a Reconfigurable Instruction Set Processor with Partial Predication and Virtual Opcode Support. 217-229
- Domingo Benitez, Juan C. Moure, Dolores Rexachs, Emilio Luque: A Reconfigurable Data Cache for Adaptive Processors. 230-242
- Daniel S. Poznanovic: The Emergence of Non-von Neumann Processors. 243-254
- Marcelo Götz, Florian Dittmann: Scheduling Reconfiguration Activities of Run-Time Reconfigurable RTOS Using an Aperiodic Task Server. 255-261
- Manuel G. Gericota, Gustavo R. Alves, Luís F. Lemos, José M. Ferreira: A New Approach to Assess Defragmentation Strategies in Dynamically Reconfigurable FPGAs. 262-267
- Minoru Watanabe, Fuminori Kobayashi: A 1, 632 Gate-Count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI. 268-273
- Stamatis Vassiliadis, Georgi Kuzmanov, Stephan Wong, Elena Moscu Panainte, Georgi Gaydadjiev, Koen Bertels, Dmitry Cheresiz: PISC: Polymorphic Instruction Set Computers. 274-286
Networks and Communication
- Sanjay Pratap Singh, Shilpa Bhoj, Dheera Balasubramanian, Tanvi Nagda, Dinesh Bhatia, Poras T. Balsara: Generic Network Interfaces for Plug and Play NoC Based Architecture. 287-298
- Nikolay Kavaldjiev, Gerard J. M. Smit, Pascal T. Wolkotte, Pierre G. Jansen: Providing QoS Guarantees in a NoC by Virtual Channel Reservation. 299-310
- Milan Tichý, Jan Schier, David Gregg: Efficient Floating-Point Implementation of High-Order (N)LMS Adaptive Filters in FPGA. 311-316
- Hongzhi Wang, Pierre Leray, Jacques Palicot: A Reconfigurable Architecture for MIMO Square Root Decoder. 317-322
Security
- Nele Mentens, Lejla Batina, Bart Preneel, Ingrid Verbauwhede: Time-Memory Trade-Off Attack on FPGA Platforms: UNIX Password Cracking. 323-334
- François-Xavier Standaert, François Macé, Eric Peeters, Jean-Jacques Quisquater: Updates on the Security of FPGAs Against Power Analysis Attacks. 335-346
- Kazuo Sakiyama, Nele Mentens, Lejla Batina, Bart Preneel, Ingrid Verbauwhede: Reconfigurable Modular Arithmetic Logic Unit for High-Performance Public-Key Cryptosystems. 347-357
- Maurice Keller, Tim Kerins, Francis M. Crowe, William P. Marnane: FPGA Implementation of a GF(2m) Tate Pairing Architecture. 358-369
- Guerric Meurice de Dormale, Jean-Jacques Quisquater: Iterative Modular Division over GF(2m): Novel Algorithm and Implementations on FPGA. 370-382
- David Rodríguez, Juan M. Sánchez, Arturo Duran: Mobile Fingerprint Identification Using a Hardware Accelerated Biometric Service Provider. 383-388
- Sherif Yusuf, Wayne Luk, M. K. N. Szeto, William G. Osborne: UNITE: Uniform Hardware-Based Network Intrusion deTection Engine. 389-400
Tools
- Betul Buyukkurt, Zhi Guo, Walid A. Najjar: Impact of Loop Unrolling on Area, Throughput and Clock Frequency in ROCCC: C to VHDL Compiler for FPGAs. 401-412
- Dinesh C. Suresh, Zhi Guo, Betul Buyukkurt, Walid A. Najjar: Automatic Compilation Framework for Bloom Filter Based Intrusion Detection. 413-418
- Jie Guo, Gleb Belov, Gerhard Fettweis: A Basic Data Routing Model for a Coarse-Grain Reconfigurable Hardware. 419-424
- Bjorn De Sutter, Bingfeng Mei, Andrei Bartic, Tom Vander Aa, Mladen Berekovic, Jean-Yves Mignolet, Kris Croes, Paul Coene, Miro Cupac, Aïssa Couvreur, Andy Folens, Steven Dupont, Bert Van Thielen, Andreas Kanstein, Hong-Seok Kim, Sukjin Kim: Hardware and a Tool Chain for ADRES. 425-430
- Jack Whitham, Neil C. Audsley: Integrating Custom Instruction Specifications into C Development Processes. 431-442
- Jens Braunes, Rainer G. Spallek: A Compiler-Oriented Architecture Description for Reconfigurable Systems. 443-448
- Antonio Carlos Schneider Beck, Victor F. Gomes, Luigi Carro: Dynamic Instruction Merging and a Reconfigurable Array: Dataflow Execution with Software Compatibility. 449-454
- Jae-Jin Lee, Gi-Yong Song: Super Semi-systolic Array-Based Application-Specific PLD Architecture. 461-466
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last updated on 2013-06-18T211851 by the dblp team