ARC 2010: Bangkok, Thailand

Keynotes (Abstracts)

• Ram Krishnamurthy:
  High-Performance Energy-Efficient Reconfigurable Accelerators/Co-processors for Tera-Scale Multi-core Microprocessors. 1
  
• Peter Y. K. Cheung:
  Process Variability and Degradation: New Frontier for Reconfigurable. 2
  
• Steven J. E. Wilton:
  Towards Analytical Methods for FPGA Architecture Investigation. 3
  

Architectures 1

• Andrés Otero, Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo:
  Generic Systolic Array for Run-Time Scalable Cores. 4-16
  
• Marc Stöttinger, Alexander Biedermann, Sorin Alexander Huss:
  Virtualization within a Parallel Array of Homogeneous Processing Units. 17-28
  
• Michael Reibel Boesen, Pascal Schleuniger, Jan Madsen:
  Feasibility Study of a Self-healing Hardware Platform. 29-41
  

Applications 1

• Martin Labrecque, Mark C. Jeffrey, J. Gregory Steffan:
  Application-Specific Signatures for Transactional Memory in Soft Processors. 42-54
  
• Christopher Claus, Rehan Ahmed, Florian Altenried, Walter Stechele:
  Towards Rapid Dynamic Partial Reconfiguration in Video-Based Driver Assistance Systems. 55-67
  
• Adrien Le Masle, Wayne Luk, Jared Eldredge, Kris Carver:
  Parametric Encryption Hardware Design. 68-79
  
• Weibo Pan, William P. Marnane:
  A Reconfigurable Implementation of the Tate Pairing Computation over GF(2^m). 80-91
  

Architectures 2

• Husain Parvez, Zied Marrakchi, Habib Mehrez:
  Application Specific FPGA Using Heterogeneous Logic Blocks. 92-109
  
• Mouna Baklouti, Philippe Marquet, Jean-Luc Dekeyser, Mohamed Abid:
  Reconfigurable Communication Networks in a Parametric SIMD Parallel System on Chip. 110-121
  
• Johann Glaser, Markus Damm, Jan Haase, Christoph Grimm:
  A Dedicated Reconfigurable Architecture for Finite State Machines. 122-133
  
• Daisaku Seto, Minoru Watanabe:
  MEMS Dynamic Optically Reconfigurable Gate Array Usable under a Space Radiation Environment. 134-144
  

Applications 2

• Abdulhadi Shoufan:
  An FPGA Accelerator for Hash Tree Generation in the Merkle Signature Scheme. 145-156
  
• Antonio Roldao Lopes, George A. Constantinides:
  A Fused Hybrid Floating-Point and Fixed-Point Dot-Product for FPGAs. 157-168
  
• David Boland, George A. Constantinides:
  Optimising Memory Bandwidth Use for Matrix-Vector Multiplication in Iterative Methods. 169-181
  
• Chalermpol Saiprasert, Christos-Savvas Bouganis, George A. Constantinides:
  Design of a Financial Application Driven Multivariate Gaussian Random Number Generator for an FPGA. 182-193
  

Design Tools 1

• Thomas Marconi, Yi Lu, Koen Bertels, Georgi Gaydadjiev:
  3D Compaction: A Novel Blocking-Aware Algorithm for Online Hardware Task Scheduling and Placement on 2D Partially Reconfigurable Devices. 194-206
  
• Karel Bruneel, Dirk Stroobandt:
  TROUTE: A Reconfigurability-Aware FPGA Router. 207-218
  
• Esam El-Araby, Vikram K. Narayana, Tarek A. El-Ghazawi:
  Space and Time Sharing of Reconfigurable Hardware for Accelerated Parallel Processing. 219-230
  
• Ganghee Lee, Seokhyun Lee, Kiyoung Choi, Nikil D. Dutt:
  Routing-Aware Application Mapping Considering Steiner Points for Coarse-Grained Reconfigurable Architecture. 231-243
  

Design Tools 2

• Hongbing Fan, Yu-Liang Wu, Chak-Chung Cheung:
  Design Automation for Reconfigurable Interconnection Networks. 244-256
  
• Kostas Siozios, Dimitrios Soudris, Dionisios N. Pnevmatikatos:
  A Framework for Enabling Fault Tolerance in Reconfigurable Architectures. 257-268
  
• S. Arash Ostadzadeh, Roel Meeuws, Carlo Galuzzi, Koen Bertels:
  QUAD - A Memory Access Pattern Analyser. 269-281
  
• Siew Kei Lam, Yun Deng, Jian Hu, Xilong Zhou, Thambipillai Srikanthan:
  Hierarchical Loop Partitioning for Rapid Generation of Runtime Configurations. 282-293
  

Applications 3

• Yu Zhang, Dan Feng:
  Reconfigurable Computing and Task Scheduling for Active Storage Service Processing. 294-305
  
• Mehdi Darouich, Stéphane Guyetant, Dominique Lavenier:
  A Reconfigurable Disparity Engine for Stereovision in Advanced Driver Assistance Systems. 306-317
  
• Mahmood Fazlali, Ali Zakerolhosseini, Georgi Gaydadjiev:
  A Modified Merging Approach for Datapath Configuration Time Reduction. 318-328
  

Posters

• Abdulhadi Shoufan, Sorin Alexander Huss:
  Reconfigurable Computing Education in Computer Science. 329-336
  
• Maciej Wielgosz, Ernest Jamro, Pawel Russek, Kazimierz Wiatr:
  Hardware Implementation of the Orbital Function for Quantum Chemistry Calculations. 337-342
  
• Suhaib A. Fahmy, Linda Doyle:
  Reconfigurable Polyphase Filter Bank Architecture for Spectrum Sensing. 343-350
  
• Kunjan Patel, Chris J. Bleakley:
  Systolic Algorithm Mapping for Coarse Grained Reconfigurable Array Architectures. 351-357
  
• Phak Len Eh Kan, Tim Allen, Steven F. Quigley:
  A GMM-Based Speaker Identification System on FPGA. 358-363
  
• Niels Penneman, Luc Perneel, Martin Timmerman, Bjorn De Sutter:
  An FPGA-Based Real-Time Event Sampler. 364-371
  
• Masato Yoshimi, Yuri Nishikawa, Mitsunori Miki, Tomoyuki Hiroyasu, Hideharu Amano, Oskar Mencer:
  A Performance Evaluation of CUBE: One-Dimensional 512 FPGA Cluster. 372-381
  
• Sergey Morozov, Abhranil Maiti, Patrick Schaumont:
  An Analysis of Delay Based PUF Implementations on FPGA. 382-387
  
• Kazuya Tanigawa, Ken'ichi Umeda, Tetsuo Hironaka:
  Comparison of Bit Serial Computation with Bit Parallel Computation for Reconfigurable Processor. 388-393
  
• Akkarat Boonpoonga, Sompop Janyavilas, Phaophak Sirisuk, Monai Krairiksh:
  FPGA Implementation of QR Decomposition Using MGS Algorithm. 394-399
  
• Kyungwook Chang, Kiyoung Choi:
  Memory-Centric Communication Architecture for Reconfigurable Computing. 400-405
  
• Lilian Janin, Shoujie Li, Doug Edwards:
  Integrated Design Environment for Reconfigurable HPC. 406-413
  
• Alok Prakash, Siew Kei Lam, Amit Kumar Singh, Thambipillai Srikanthan:
  Architecture-Aware Custom Instruction Generation for Reconfigurable Processors. 414-419
  
• Victoria Rodellar, Elvira Martínez de Icaya, Francisco Díaz, Virginia Peinado:
  Cost and Performance Evaluation of a Noise Filter for Partitioning in Co-design Methodologies. 420-425
  
• Harald Devos, Wim Meeus, Dirk Stroobandt:
  Towards a Tighter Integration of Generated and Custom-Made Hardware. 426-434
  
• Bijan Alizadeh, Amir Masoud Gharehbaghi, Masahiro Fujita:
  Pipelined Microprocessors Optimization and Debugging. 435-444
  

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