ARVLSI 1995: Chapel Hill, North Carolina, USA
16th Conference on Advanced Research in VLSI (ARVLSI '95), March 27-29, 1995, Chapel Hill, North Carolina, USA. IEEE Computer Society 1995- Peter M. Kogge, Toshio Sunaga, Hisatada Miyataka, Koji Kitamura, Eric Retter: Combined DRAM and logic chip for massively parallel systems. 4-16
- Huy Cat, Myunghee Lee, Brent Buchanan, D. Scott Wills, Martin A. Brooke, Nan M. Jokerst: Silicon VLSI processing architectures incorporating integrated optoelectronic devices. 17-27
- M. Bolotski, T. Simon, C. Vieri, R. Amirtharajah, Thomas F. Knight Jr.: Abacus: a 1024 processor 8 ns SIMD array. 28-41
- Chris J. Myers, Tomas Rokicki, Teresa H. Y. Meng: Automatic synthesis of gate-level timed circuits with choice. 42-58
- Robert M. Fuhrer, Bill Lin, Steven M. Nowick: Algorithms for the optimal state assignment of asynchronous state machines. 59-75
- Erik Brunvand: Low latency self-timed flow-through FIFOs. 76-90
- Jae-Tack Yoo, Ganesh Gopalakrishnan, Kent F. Smith, V. John Mathews: High speed counterflow-clocked pipelining illustrated on the design of HDTV subband vector quantizer chips. 91-107
- Gert Cauwenberghs: Bit-serial bidirectional A/D/A conversio. 108-120
- Hans Lindkvist, Per Andersson: Dynamic CMOS circuit techniques for delay and power reduction in parallel adders . 121-130
- Gary C. Moyer, Mark Clements, Wentai Liu, Toby Schaffer, Ralph K. Cavin III: A technique for high-speed, fine-resolution pattern generation and its CMOS implementation. 131-149
- H. Dhanesha, K. Falakshahi, Mark Horowitz: Array-of-arrays architecture for parallel floating point multiplication. 150-157
- X. Cai, Keith Nabors, Jacob White: Efficient Galerkin techniques for multipole-accelerated capacitance extraction of 3-D structures with multiple dielectrics. 200-213
- Alex G. Dickinson, Bryan D. Ackland, El-Sayed Eid, David A. Inglis, Eric R. Fossum: Standard CMOS active pixel image sensors for multimedia applications. 214-224
- Andreas G. Andreou, Kwabena Boahen: A 590, 000 transistor 48, 000 pixel, contrast sensitive, edge enhancing, CMOS imager-silicon retina. 225-240
- Tonia G. Morris, Denise M. Wilson, Stephen P. DeWeerth: Analog VLSI circuits for manufacturing inspection. 241-257
- Huy Nguyen, Abhijit Chatterjee: OPTIMUS: a new program for OPTIMizing linear circuits with number-splitting and shift-and-add decompositions. 258-271
- Stan Y. Liao, Srinivas Devadas, Kurt Keutzer: Code density optimization for embedded DSP processors using data compression techniques. 272-285
- Timothy J. Stanley, Trevor N. Mudge: Systematic objective-driven computer architecture optimization. 286-303
- Larry R. Dennison, William J. Dally, Thucydides Xanthopoulos: Low-latency plesiochronous data retiming. 304-315
- José Monteiro, John Rinderknecht, Srinivas Devadas, Abhijit Ghosh: Optimization of combinational and sequential logic circuits for low power using precomputation. 430-444
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