ARVLSI 1999: Atlanta, GA, USA

• Charles L. Seitz:
  Silicon Adventures-Go Ahead; Be Bold! 2
  
• Bruce R. Childers, Jack W. Davidson:
  Architectural Considerations for Application-Specific Counterflow Pipelines. 3-22
  
• Darren C. Cronquist, Chris Fisher, Miguel Figueroa, Paul Franklin, Carl Ebeling:
  Architecture Design of Reconfigurable Pipelined Datapaths. 23-41
  
• Tonia Morris, Erica Fletcher, Cyrus Afghahi, Sami Issa, Kevin Connolly, Jean-Charles Korta:
  A Column-based Processing Array for High-speed Digital Image Processing. 42-56
  
• Sek M. Chai, Antonio Gentile, D. Scott Wills:
  Impact of Power Density Limitation in Gigascale Integration for the SIMD Pixel Processor. 57-71
  
• Kwabena Boahen:
  A Throughput-On-Demand Address-Event Transmitter for Neuromorphic Chips. 72-87
  
• James D. Meindl:
  XXI Century Gigascale Integration (GSI) : The Interconnect Problem. 88-
  
• Sandeep N. Bhatt, Gianfranco Bilardi, Geppino Pucci:
  Area-Universal Circuits with Constant Slowdown. 89-98
  
• Spencer M. Gold, Richard B. Brown, Bruce Bernhardt:
  A Quantitative Approach to Nonlinear Process Design Rule Scaling. 99-113
  
• P. Ghosh, R. Mangaser, C. Mark, K. Rose:
  Interconnect-Dominated VLSI Design. 114-122
  
• Li-Rong Zheng, Hannu Tenhunen:
  Noise Margin Constraints for Interconnectivity in Deep Submicron Low Power and Mixed-Signal VLSI Circuits. 123-136
  
• Nestoras Tzartzanis, William C. Athas:
  Clock-Powered CMOS: A Hybrid Adiabatic Logic Style for Energy-Efficient Computing. 137-153
  
• Robert W. Brodersen:
  System-on-a-Chip VLSI - Is It Finally Really Here? 154-
  
• Ching-Wei Yeh, Min-Cheng Chang, Yin-Shuin Kang:
  Algorithms Promoting the Use of Dual Supply Voltages for Power-Driven Designs. 155-169
  
• Vijay Sundararajan, Keshab K. Parhi:
  Low Power Gate Resizing of Combinational Circuits by Buffer-Redistribution. 170-185
  
• Bradley A. Minch:
  Translinear Analog Signal Processing: A Modular Approach to Large-Scale Analog Computation with Multiple-Input Translinear Elements. 186-199
  
• Ayoob E. Dooply, Kenneth Y. Yun:
  Optimal Clocking and Enhanced Testability for High-Performance Self-Resetting Domino Pipelines. 200-214
  
• Paul E. Hasler, Bradley A. Minch, Chris Diorio:
  Adaptive Circuits Using pFET Floating-Gate Devices. 215-231
  
• William J. Dally, Steve Lacy:
  VLSI Architecture: Past, Present, and Future. 232-241
  
• Lucian Codrescu, Mondira Deb Pant, Tarek M. Taha, John Eble, D. Scott Wills, James D. Meindl:
  Exploring Microprocessor Architectures for Gigascale Integration. 242-255
  
• Dana S. Henry, Bradley C. Kuszmaul, Vinod Viswanath:
  The Ultrascalar Processor-An Asymptotically Scalable Superscalar Microarchitecture. 256-275
  
• Timothy K. Horiuchi, Ernst Niebur:
  Conjunction Search Using a 1-D, Analog VLSI-based, Attentional Search/Tracking Chip. 276-290
  
• Charles S. Wilson, Tonia G. Morris, Stephen P. DeWeerth:
  A Two-Dimensional, Object-Based Analog VLSI Visual Attention System. 291-308
  
• Charles M. Higgins, Christof Koch:
  Multi-Chip Neuromorphic Motion Processing. 309-325
  
• John Poulton:
  Problems and Prospects for Electrical Signaling. 326-
  
• Sudip Chakrabarti, Abhijit Chatterjee:
  Compact Fault Dictionary Construction for Efficient Isolation of Faults in Analog and Mixed-Signal Circuits. 327-341
  
• Ramakrishna Voorakaranam, Abhijit Chatterjee:
  Feedback Driven Backtrace of Analog Signals and its Application to Circuit Verification and Test. 342-357
  
• Neil Weste:
  Who Put the Sugar in Sydney Harbor?. 358-
  
• Charles L. Britton Jr., R. J. Warmack, S. F. Smith, A. L. Wintenberg, T. Thundat, G. M. Brown, W. L. Bryan, J. C. Depriest, M. Nance Ericson, M. S. Emery, M. R. Moore, G. W. Turner, L. G. Clonts, R. L. Jones, T. D. Threatt, Z. Hu, James M. Rochelle:
  Battery-powered, Wireless MEMS Sensors for High-Sensitivity Chemical and Biological Sensing. 359-368
  
• B. E. Duewer, J. M. Wilson, D. A. Winick, Paul D. Franzon:
  MEMS-Based Capacitor Arrays for Programmable Interconnect and RF Applications. 369-377
  

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