ASAP 2007: Montréal, Québec, Canada

• Steven Derrien, Patrice Quinton:
  Parallelizing HMMER for Hardware Acceleration on FPGAs. 10-17
  
• Shuli Gao, Noureddine Chabini, Dhamin Al-Khalili, J. M. Pierre Langlois:
  FPGA-Based Efficient Design Approach for Large-Size Two's Complement Squarers. 18-23
  
• Antonino Tumeo, Matteo Monchiero, Gianluca Palermo, Fabrizio Ferrandi, Donatella Sciuto:
  A Self-Reconfigurable Implementation of the JPEG Encoder. 24-29
  
• Jahyun J. Koo, David Fernández, Ashraf Haddad, Warren J. Gross:
  Evaluation of a High-Level-Language Methodology for High-Performance Reconfigurable Computers. 30-35
  
• Kai Huang, D. Grunert, Lothar Thiele:
  Windowed FIFOs for FPGA-based Multiprocessor Systems. 36-41
  
• Haibo Zhu, Partha Pratim Pande, Cristian Grecu:
  Performance Evaluation of Adaptive Routing Algorithms for achieving Fault Tolerance in NoC Fabrics. 42-47
  
• Mohammad Abdullah Al Faruque, Jörg Henkel:
  Transaction Specific Virtual Channel Allocation in QoS Supported On-chip Communication. 48-53
  
• Abdellah-Medjadji Kouadri-Mostefaoui, Benaoumeur Senouci, Frédéric Pétrot:
  Scalable Multi-FPGA Platform for Networks-On-Chip Emulation. 54-60
  
• Gianluca Palermo, Giovanni Mariani, Cristina Silvano, Riccardo Locatelli, Marcello Coppola:
  Mapping and Topology Customization Approaches for Application-Specific STNoC Designs. 61-68
  
• Sumit D. Mediratta, Jeffrey T. Draper:
  Performance Evaluation of Probe-Send Fault-tolerant Network-on-chip Router. 69-75
  
• Nhut Thanh Quach, Bahman Zafarifar, Georgi Gaydadjiev:
  Real-time FPGA-implementation for blue-sky Detection. 76-82
  
• Nikhil Kikkeri, Peter-Michael Seidel:
  An FPGA Implementation of a Fully Verified Double Precision IEEE Floating-Point Adder. 83-88
  
• Siew Kei Lam, Thambipillai Srikanthan:
  Estimating Area Costs of Custom Instructions for FPGA-based Reconfigurable Processors. 89-94
  
• Yong Dou, Jie Zhou, Yuanwu Lei, Xingming Zhou:
  FPGA SAR Processor with Window Memory Accesses. 95-100
  
• Sherman Braganza, Miriam Leeser:
  The 1D Discrete Cosine Transform For Large Point Sizes Implemented On Reconfigurable Hardware. 101-106
  
• Panagiotis D. Vouzis, Sylvain Collange, Mark G. Arnold:
  LNS Subtraction Using Novel Cotransformation and/or Interpolation. 107-114
  
• Charles Tsen, Michael J. Schulte, Sonia Gonzalez-Navarro:
  Hardware Design of a Binary Integer Decimal-based IEEE P754 Rounding Unit. 115-121
  
• Milos D. Ercegovac, Jean-Michel Muller:
  A Hardware-Oriented Method for Evaluating Complex Polynomials. 122-127
  
• Eric M. Schwarz, Steven R. Carlough:
  Power6 Decimal Divide. 128-133
  
• Pramod Kumar Meher:
  Systolic Formulation for Low-Complexity Serial-Parallel Implementation of Unified Finite Field Multiplication over GF(2^m). 134-139
  
• Alain Darte, C. Quinson:
  Scheduling Register-Allocated Codes in User-Guided High-Level Synthesis. 140-147
  
• A. Aguiar, M. Kreutz, R. Santos, T. Santos:
  Design Flow of a Dedicated Computer Cluster Customized for a Distributed Genetic Algorithm Application. 148-153
  
• Amirhossein Alimohammad, Saeed Fouladi Fard, Bruce F. Cockburn, Christian Schlegel:
  A Compact Fading Channel Simulator Using Timing-Driven Resource Sharing. 154-159
  
• K. Nibbelink, S. Rajopadhye, R. McConnell:
  0/1 Knapsack on Hardware: A Complete Solution. 160-167
  
• David B. Thomas, Jacob A. Bower, Wayne Luk:
  Automatic Generation and Optimisation of Reconfigurable Financial Monte-Carlo Simulations. 168-173
  
• Asadollah Shahbahrami, Ben H. H. Juurlink, Stamatis Vassiliadis:
  SIMD Vectorization of Histogram Functions. 174-179
  
• Wei-Ting Wang, Yi-Chi Chen, Chung-Ping Chung:
  A Run-Time Reconfigurable Fabric for 3D Texture Filtering. 180-185
  
• Humberto Calderon, Georgi Gaydadjiev, Stamatis Vassiliadis:
  Reconfigurable Universal Adder. 186-191
  
• Feng Shi, Weixing Ji, Baojun Qiao, Bin Liu, Haroon-ul-Rashid:
  A Triplet-based Computer Architecture Supporting Parallel Object Computing. 192-197
  
• Weixing Ji, Feng Shi, Baojun Qiao, Muhammad Kamran:
  The Design of a Novel Object-oriented Processor : OOMIPS. 198-203
  
• Siavash Bayat Sarmadi, M. Anwar Hasan:
  Run-Time Error Detection in Polynomial Basis Multiplication Using Linear Codes. 204-209
  
• Jae Young Hur, Todor Stefanov, Stephan Wong, Stamatis Vassiliadis:
  Customizing Reconfigurable On-Chip Crossbar Scheduler. 210-215
  
• Hau T. Ngo, Satyanadh Gundimada, Vijayan K. Asari:
  Design and Implementation of an Efficient and Power-Aware Architecture for Skin Segmentation in Color Video Stream. 216-221
  
• Roberto R. Osorio, Javier D. Bruguera:
  Entropy Coding on a Programmable Processor Array for Multimedia SoC. 222-227
  
• Xiongfei Liao, Wu Jigang, Thambipillai Srikanthan:
  Temperature-Aware Submesh Allocation Scheme for Heat Balancing on Chip-Multiprocessors. 228-233
  
• C. Boustany, Ahmed Lakhsasi, Mohammed Bougataya:
  Design and implementation of a surface peak thermal detector algorithm. 234-238
  
• Marcel Bimberg, Marcos B. S. Tavares, Emil Matús, Gerhard Fettweis:
  A High-Throughput Programmable Decoder for LDPC Convolutional Codes. 239-246
  
• Maria G. Koziri, A. N. Dadaliaris, Georgios I. Stamoulis, Ioannis Katsavounidis:
  A Novel Low-Power Motion Estimation Design for H.264. 247-252
  
• Liang Lu, John V. McCanny, Sakir Sezer:
  Reconfigurable Motion Estimation Architecture for Multi-standard Video Compression. 253-259
  
• Jianying Peng, Xing Qin, Dexian Li, Xiaolang Yan, Xiexiong Chen:
  An Efficient SIMD Architecture with Parallel Memory for 2D Cosine Transforms of Video Coding. 260-265
  
• A. A. Bayrakci, A. Akkas:
  Reduced Delay BCD Adder. 266-271
  
• Julio Villalba, Javier Hormigo, Tomás Lang:
  Improving the Throughput of On-line Addition for Data Streams. 272-277
  
• Walid Ibrahim, Valeriu Beiu:
  Long Live Small Fan-in Majority Gates Their Reign Looks Like Coming! 278-283
  
• D. K. Wilde:
  Computing Digit Selection Regions for Digit Recurrences. 284-289
  
• Bo Zhou, Xiaobo Sharon Hu, Danny Z. Chen, Cedric X. Yu:
  Hardware Acceleration for 3-D Radiation Dose Calculation. 290-295
  
• Götz Kappen, S. el Bahri, O. Priebe, Tobias G. Noll:
  Evaluation of a Tightly Coupled ASIP / Co-Processor Architecture Used in GNSS Receivers. 296-301
  
• Stephan Bourduas, Zeljko Zilic:
  Latency Reduction of Global Traffic in Wormhole-Routed Meshes Using Hierarchical Rings for Global Routing. 302-307
  
• Ben Cope, Peter Y. K. Cheung, Wayne Luk:
  Bridging the Gap between FPGAs and Multi-Processor Architectures: A Video Processing Perspective. 308-313
  
• Youcef Bouchebaba, Essaid Bensoudane, Bruno Lavigueur, Pierre G. Paulin, Gabriela Nicolescu:
  Two-level tiling for MPSoC architecture. 314-319
  
• Suman Mamidi, Michael J. Schulte, Daniel Iancu, C. John Glossner:
  Architecture Support for Reconfigurable Multithreaded Processors in Programmable Communication Systems. 320-327
  
• Christophe Wolinski, Krzysztof Kuchcinski:
  Identification of Application Specific Instructions Based on Sub-Graph Isomorphism Constraints. 328-333
  
• Paolo Bonzini, Laura Pozzi:
  A Retargetable Framework for Automated Discovery of Custom Instructions. 334-341
  
• Mahzad Azarmehr, Roberto Muscedere:
  A Simple Central Processing Unit with Multi-Dimensional Logarithmic Number System Extensions. 342-345
  
• Jie Guo, Jun Liu, Björn Mennenga, Gerhard Fettweis:
  A Phase-Coupled Compiler Backend for a New VLIW Processor Architecture Using Two-step Register Allocation. 346-352
  
• Sadaf R. Alam, Jeffrey S. Vetter, Melissa C. Smith:
  An Application Specific Memory Characterization Technique for Co-processor Accelerators. 353-358
  
• Ning Qu, Yansong Zheng, Wei Cao, Xu Cheng:
  GISP: A Transparent Superpage Support Framework for Linux. 359-364
  
• David Montgomery, Ali Akoglu:
  Methodology and Toolset for ASIP Design and Development Targeting Cryptography-Based Applications. 365-370
  
• Zhixiong Zhou, Hu He, Yanjun Zhang, Yihe Sun, Adriel Cheng:
  A 2-Dimension Force-Directed Scheduling Algorithm for Register-File-Connectivity Clustered VLIW Architecture. 371-376
  
• Sylvain Collange, Marc Daumas, David Defour:
  Graphic processors to speed-up simulations for the design of high performance solar receptors. 377-382
  
• Imyong Lee, Dongwook Lee, Kiyoung Choi:
  Memory Operation Inclusive Instruction-Set Extensions and Data Path Generation. 383-390
  
• Ismo Hänninen, Jarmo Takala:
  Robust Adders Based on Quantum-Dot Cellular Automata. 391-396
  
• Filipa Duarte, Stephan Wong:
  A memcpy Hardware Accelerator Solution for Non Cache-line Aligned Copies. 397-402
  
• D. A. Armstrong, M. W. Pearson:
  A Rapid Prototyping Platform for Wireless Medium Access Control Protocols. 403-408
  
• Yong-Joon Park, Zhao Zhang, Gyungho Lee:
  An Efficient Hardware Support for Control Data Validation. 409-414
  
• William Josephson, Ruby B. Lee, Kai Li:
  ISA Support for Fingerprinting and Erasure Codes. 415-422
  

Last update Mon May 21 02:22:01 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page