ASP-DAC 1995: Makuhari, Massa, Chiba, Japan

• Wen-Zen Shen, Jiing-Yuan Lin, Fong-Wen Wang:
  Transistor reordering rules for power reduction in CMOS gates.
  
• How-Rern Lin, TingTing Hwang:
  Power recduction by gate sizing with path-oriented slack calculation.
  
• Sanjay Dhar, Dave J. Gurney:
  Current and charge estimation in CMOS circuits.
  
• J. P. Tual, M. Thill, C. Bernard, Huy Nam Nguyen, F. Mottini, M. Moreau, P. Vallet:
  Auriga2: a 4.7 million-transistor CISC microprocessor.
  
• Hiroaki Kunieda, Yusong Liao, Dongju Li, Kazuhito Ito:
  Automatic design for bit-serial MSPA architecture.
  
• Ivanil S. Bonatti, Renato J. O. Figueiredo:
  Stoht: an SDL-to-hardware translator.
  
• Vasily G. Moshnyaga, Fumiaki Ohbayashi, Keikichi Tamaru:
  A scheduling algorithm for synthesis of bus-partitioned architectures.
  
• Richard K. Wallace:
  Design automation 2000 (panel session): challenges for gigabit-era.
  
• Pradip K. Jha, Nikil D. Dutt, Sri Parameswaran:
  Reclocking for high-level synthesis.
  
• Shih-Hsu Huang, Ta-Yung Liu, Yu-Chin Hsu, Yen-Jen Oyang:
  Synthesis of false loop free circuits.
  
• Marc J. M. Heijligers, L. J. M. Cluitmans, Jochen A. G. Jess:
  High-level synthesis scheduling and allocation using genetic algorithms.
  
• C.-J. Richard Shi, Janusz A. Brzozowski:
  A framework for the analysis and design of algorithms for a class of VLSI-CAD optimization problems.
  
• Eric Q. Kang, Eugene Shragowitz:
  Generic fuzzy logic CAD development tool.
  
• Nguyen-Ngoc Bình, Masaharu Imai, Akichika Shiomi, Nobuyuki Hikichi:
  A hardware/software codesign method for pipelined instruction set processor using adaptive database.
  
• Wen-Jong Fang, Allen C.-H. Wu, Tsing-Gen Lee:
  EMPAR: an interactive synthesis environment for hardware emulations.
  
• Hae-Dong Lee, Sun-Young Hwang:
  A scheduling algorithm for multiport memory minimization in datapath synthesis.
  
• Yongjoo Kim, Kyuseok Kim, Youngsoo Shin, Taekyoon Ahn, Wonyong Sung, Kiyoung Choi, Soonhoi Ha:
  An integrated hardware-software cosimulation environment for heterogeneous systems prototyping.
  
• J. Y. Lim, G. Kim, I.-S. O, J. H. Cho, Y. Kim, H. Y. Kim:
  A CSIC implementation with POCSAG decoder and microcontroller for paging applications.
  
• Chunghee Kim, Hyunchul Shin, Young-Uk Yu:
  Performance-driven circuit partitioning for prototyping by using multiple FPGA chips.
  
• Yoshinori Katsura, Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida:
  A new system partitioning method under performance and physical constraints for multi-chip modules.
  
• Katsunori Tani:
  A robust min-cut improvement algorithm based on dynamic look-ahead weighting.
  
• Sadiq M. Sait, Habib Youssef, Shahid K. Tanvir, Muhammad S. T. Benten:
  Timing influenced generell-cell genetic floorplanner.
  
• Vivek Tiwari, Mike Tien-Chien Lee:
  Power analysis of a 32-bit embedded microcontroller.
  
• Marco A. Escalante, Nikitas J. Dimopoulos:
  Assessing the feasibility of interface designs before their implementation.
  
• A. Ghosh, M. Bershteyn, R. Casley, C. Chien, A. Jain, M. Lipsie, D. Tarrodaychik, O. Yamamo:
  A hardware-software co-simulator for embedded system design and debugging.
  
• Won-Young Jung, Ghun-Up Cha, Young-Bae Kim, Jun-Ho Baek, Choon-Kyung Kim:
  Integrated interconnect circuit modeling for VLSI design.
  
• Jong Tae Lee, Jaemin Kim, Jae Cheol Son:
  Architectural simulation for a programmable DSP chip set.
  
• Gyeong Lyong Park, Kyung Hi Chang, Jae Seok Kim, Kyung Soo Kim:
  System-level verification of CDMA modem ASIC.
  
• Jeongsik Yang, Chanhong Park, Beomsup Kim:
  A digital audio signal processor for cellular phone application.
  
• Jin-Tai Yan:
  Region definition and ordering assignment with the minimization of the number of switchboxes.
  
• Masahiro Tsuchiya, Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida:
  A three-layer over-cell multi-channel routing method for a new cell model.
  
• Man-Fai Yu, Wayne Wei-Ming Dai:
  Pin assignment and routing on a single-layer Pin Grid Array.
  
• Akira Motohara, Sadami Takeoka, Toshinori Hosokawa, Mitsuyasu Ohta, Yuji Takai, Michihiro Matsumoto, Michiaki Muraoka:
  Design for testability using register-transfer level partial scan selection.
  
• T. Raju Damarla, Wei Su, Gerald T. Michael, Moon J. Chung, Charles E. Stroud:
  A built-in self test scheme for VLSI.
  
• T. Bogue, Helmut Jürgensen, Michael Gössel:
  BIST with negligible aliasing through random cover circuits.
  
• Hiroyuki Higuchi, Yusuke Matsunaga:
  Implicit prime compatible generation for minimizing incompletely specified finite state machines.
  
• Uwe Gläser, Kwang-Ting Cheng:
  Logic optimization by an improved sequential redundancy addition and removal techniques.
  
• Alex Kondratyev, Michael Kishinevsky, Alexandre Yakovlev:
  On hazard-free implementation of speed-independent circuits.
  
• Hiroshi Miyashita:
  Extending pitchmaking algorithms to layouts with multiple grid constraints.
  
• Masahiro Fukui, Noriko Shinomiya, Toshiro Akino:
  A new layout synthesis for leaf cell design.
  
• Akira Nagao, Chiyoshi Yoshioka, Takashi Kambe, Isao Shirakawa:
  A layout approach to Monolithic Microwave IC.
  
• Chia-Chun Tsai, De-Yu Kao, Chung-Kuan Cheng, Ting-Ting Y. Lin:
  Performance driven multiple-source bus synthesis using buffer insertion.
  
• Christoph Scholl, Paul Molitor:
  Communication based FPGA synthesis for multi-output Boolean functions.
  
• José M. Quintana, Maria J. Avedillo, Maria P. Parra, José L. Huertas:
  Optimum PLA folding through boolean satisfiability.
  
• Jung-Yong Lee, Eugene Shragowitz:
  Technology mapping for FPGAs with complex block architectures by fuzzy logic techniques.
  
• Chih-Chang Lin, David Ihsin Cheng, Malgorzata Marek-Sadowska, Kuang-Chien Chen:
  Logic rectification and synthesis for engineering change.
  
• Masaharu Imai, Eugenio Villar:
  Future direction of synthesizability and interoperability of HDL's: part 1.
  
• Bernhard M. Riess, Heiko A. Giselbrecht, Bernd Wurth:
  A new K-way partitioning approach for multiple types of FPGAs.
  
• Nozomu Togawa, Masao Sato, Tatsuo Ohtsuki:
  Maple-opt: a simultaneous technology mapping, placement, and global routing algorithm FPGAs with performance optimization.
  
• Yu-Liang Wu, Malgorzata Marek-Sadowska:
  Routing on regular segmented 2-D FPGAs.
  
• Chip-Hong Chang, Bogdan J. Falkowski:
  Flexible optimization of fixed polarity Reed-Muller expansions for multiple and output completely and incompletely specified boolean functions.
  
• Debatosh Debnath, Tsutomu Sasao:
  GRMIN: a heuristic simplification algorithm for generalized Reed-Muller expressions.
  
• Rolf Drechsler, Bernd Becker:
  Learning heuristics by genetic algorithms.
  
• Shigeru Yamashita, Yahiko Kambayashi, Saburo Muroga:
  Optimization methods for lookup-table-based FPGAs using transduction method.
  
• Eugenio Villar, Masaharu Imai:
  Future direction of synthesizabilty and interoperability of HDL's: part 2.
  
• Denis Deschacht, Christophe Dabrin:
  A new and accurate interconnection delay time evaluation in a general tree-type network.
  
• Mikako Miyama, Goichi Yokomizo, Masato Iwabuchi, Masami Kinoshita:
  An efficient logic/circuit mixed-mode simulator for analysis of power supply voltage fluctutation.
  
• Hitoshi Yoshizawa:
  How sub-micron delay and timing issues will be solved?
  
• Masaki Kondo, Hidetoshi Onodera, Keikichi Tamaru:
  A model-adaptable MOSFET parameter extraction system.
  
• Per Lindgren:
  Improved computational methods and lazy evaluation of the Ordered Ternary Decision Diagram.
  
• Radomir S. Stankovic:
  Some remarks about spectral transform interpretation of MTBDDs and EVBDDs.
  
• Shinya Ishihara, Shin-ichi Minato:
  Manipulation of regular expressions under length constraints using zero-suppressed-BDDs.
  
• Jason Cong, Dongmin Xu:
  Exploitation signal flow and logic dependency in standard cell placement.
  
• Tetsushi Koide, Mitsuhiro Ono, Shin'ichi Wakabayashi, Yutaka Nishimaru:
  A new performance driven placement method with the Elmore delay model for row based VLSIs.
  
• Morteza Saheb Zamani, Graham R. Hellestrand:
  A neural network approach to the placement problem.
  
• T. Aoki, Masami Murakata, Takashi Mitsuhashi, Nobuyuki Goto:
  Fanout-tree restructuring algorithm for post-placement timing optimization.
  
• Hiroshi Uno, Toru Chiba, Keiji Kumatani, Isao Shirakawa:
  Synthesis and simulation of digital demodulator for infrared data communication.
  
• Hilary J. Kahn:
  EDIF version 350/400 and information modeling.
  
• Keisuke Okada, Shun Morikawa, Isao Shirakawa, Sumitaka Takeuchi:
  A design of high-performance multiplier for digital video transmission.
  
• Kazuyuki Wada, Shigetaka Takagi, Zdzislaw Czarnul, Nobuo Fujii:
  Design automation for integrated continuous-time filters using integrators.
  
• Chun-Te Chen, Liang-Gee Chen, Jue-Hsuan Hsiao:
  A hardware-oriented design for weighted median filters.
  
• Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh:
  Techniques for low power realization for FIR filters.
  
• Noriya Kobayashi, Sharad Malik:
  Delay abstraction in combinational logic circuits.
  
• Janett Mohnke, Paul Molitor, Sharad Malik:
  Limits of using signatures for permutation independent Boolean comparison.
  
• Takashi Aoki, Tomoji Toriyama, Kenji Ishikawa, Kennosuke Fukami:
  A tool for measuring quality of test pattern for LSIs' functional design.
  
• Atsushi Masuda, Hiroshi Imai, Jeffery P. Hansen, Masatoshi Sekine:
  Search space reduction in high level synthesis by use of an initial circuit.
  
• Reiner W. Hartenstein, Rainer Kress:
  A datapath synthesis system for the reconfigurable datapath architecture.
  
• Miodrag Potkonjak, Sujit Dey, Rabindra K. Roy:
  Synthesis-for-testability using transformations.
  
• Kinya Tabuchi:
  Electronic data book: current status of standard representation and future perspective.
  

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