ASP-DAC 1999: Hong Kong

Analog CAD

• Xiang-Dong Tan, C.-J. Richard Shi:
  Balanced Multi-Level Multi-Way Partitioning of Large Analog Circuits for Hierarchical Symbolic Analysis. 1-4
  
• Youcef Bourai, C.-J. Richard Shi:
  Symmetry Detection for Automatic Analog-Layout Recycling. 5-8
  
• Huazhong Yang, Rong Luo, Hui Wang, Runsheng Liu:
  An SA-Based Nonlinear Function Synthesizer for Linear Analog Integrated Circuits. 9-
  

Physical Design 1 - Floorplanning

• Jason Cong, Tianming Kong, Dongmin Xu, Faming Liang, Jun S. Liu, Wing Hung Wong:
  Relaxed Simulated Tempering for VLSI Floorplan Designs. 13-16
  
• Fung Yu Young, D. F. Wong:
  Slicing Floorplans with Boundary Constraint. 17-20
  
• Xiaohai Wu, Changge Qiao, Xianlong Hong:
  Design and Optimization of Power/Ground Network for Cell-Based VLSIs with Macro Cells. 21-
  

Design Contest

• Ju-Hyung Kim, Sung-Wook Hwang, Seung-Hoon Lee, Yong Jee:
  An 8b 52MHz Double-Channel CMOS A/D Converter for High-Speed Data Communications. 25-28
  
• Byeong-Lyeol Jeon, Kang-Jin Lee, Seung-Hoon Lee, Sang-Won Yoon:
  A 10b 50 MHz CMOS A/D Converter for High-Speed Video Applications. 29-32
  
• Byung-Soo Choi, Dong-Wook Lee, Dong-Ik Lee:
  The Design of Delay Insensitive Asynchronous 16-bit Microprocessor. 33-36
  
• Shin'ichi Wakabayashi, Tetsushi Koide, Naoyoshi Toshine, Mutsuaki Goto, Yoshikatsu Nakayama, Koichi Hatta:
  An LSI Implementation of an Adaptive Genetic Algorithm with On-The Fly Crossover Operator Selection. 37-40
  
• Li Jiang, Dongju Li, Shintaro Haba, Chawalit Honsawek, Hiroaki Kunieda:
  Motion Estimator LSI for MPEG2 High Level Standard. 41-44
  
• Jin-Kug Lee, Dong-Young Chang, Geun-Soon Kang, Seung-Hoon Lee:
  A Single-Chip CMOS CCD Camera Interface Circuit with Digitally Controlled AGC. 45-48
  
• Tae Hun Kim, Jeongsik Yang, Kyoo Hyun Lim, Jin Wook Kim, Jeong Eun Lee, Hyoung Sik Nam, Young Gon Kim, Jeong Pyo Kim, Sang Lin Byun, Bae Sung Kwon, Beomsup Kim:
  16-bit DSP and System for Baseband / Voiceband Processing of IS-136 Cellular Telephony. 49-
  

Circuit Simulation 1

• Jaijeet S. Roychowdhury:
  Reduced-Order Modelling of Time-Varying Systems. 53-56
  
• Onuttom Narayan, Jaijeet S. Roychowdhury:
  Analysing Forced Oscillators with Multiple Time Scales. 57-60
  
• Yao-Lin Jiang, Omar Wing:
  Waveform Relaxation of Linear Integral-Differential Equations for Circuit Simulation. 61-64
  
• Mark M. Gourary, Sergey G. Rusakov, Sergey L. Ulyanov, Michael M. Zharov, Kiran K. Gullapalli, Brian J. Mulvaney:
  A New Technique to Exploit Frequency Domain Latency in Harmonic Balance Simulators. 65-
  

Physical Design 2 - Partitioning

• Jong-Sheng Cherng, Sao-Jie Chen, Chia-Chun Tsai, Jan-Ming Ho:
  An Efficient Two-Level Partitioning Algorithm for VLSI Circuits. 69-72
  
• C. K. Eem, J. W. Chong:
  An Efficient Iterative Improvement Technique for VLSI Circuit Partitioning Using Hybrid Bucket Structures. 73-76
  
• Shiuann-Shiuh Lin, Wen-Hsin Chen, Wen-Wei Lin, TingTing Hwang:
  A Clustering Based Linear Ordering Algorithm for K-Way Spectral Partitioning. 77-80
  
• Jan-Yang Chang, Yu-Chen Liu, Ting-Chi Wang:
  Faster and Better Spectral Algorithms for Multi-Way Partitioning. 81-
  

Circuit Simulation 2

• Masayuki Takahashi, Kimihiro Ogawa, Kenneth S. Kundert:
  VCO Jitter Simulation and Its Comparison With Measurement. 85-88
  
• Hui Zheng, Wenjun Zhang, Lilin Tian, Zhilian Yang:
  Enhancing the Efficiency of Reduction of Large RC networks By Pole Analysis via Congruence Transformations. 89-92
  
• Jinsong Hou, Zeyi Wang, Xianlong Hong:
  The Hierarchical h-Adaptive 3-D Boundary Element Computation of VLSI Interconnect Capacitance. 93-
  

Physical Design 3 - Interconnection

• Jason Cong, David Zhigang Pan:
  Interconnect Delay Estimation Models for Synthesis and Design Planning. 97-100
  
• Feng Zhou, Zhijun Huang, Jiarong Tong, Pushan Tang:
  An Analytical Delay Model for SRAM-Based FPGA Interconnections. 101-104
  
• Shihliang Ou, Massoud Pedram:
  Timing-Driven Bipartitioning with Replication Using Iterative Quadratic Programming. 105-108
  
• Massoud Pedram, Chi-Ying Tsui, Qing Wu:
  An Integrated Battery-Hardware Model for Portable Electronics. 109-
  

Circuit 1 - Low-power/High-speed

• Shinichiro Mutoh, Satoshi Shigematsu, Yoshinori Gotoh, Shinsuke Konaka:
  Design Method of MTCMOS Power Switch for Low-Voltage High-Speed LSIs. 113-116
  
• Young-Su Kwon, Bong-Il Park, In-Cheol Park, Chong-Min Kyung:
  A New Single-Clock Flip-Clop for Half-Swing Clocking. 117-120
  
• Kenneth Y. Yun, Ayoob E. Dooply:
  Optimal Evaluation Clocking of Self-Resetting Domino Pipelines. 121-124
  
• Tomoyuki Yoda, Atsushi Takahashi, Yoji Kajitani:
  Clock Period Minimization of Semi-Synchronous Circuits by Gate-Level Delay Insertion. 125-
  

Physical Design 4 - Analog, Noise

• Dongsheng Wang, Ping Zhang, Chung-Kuan Cheng, Arunabha Sen:
  A Performance-Driven I/O Pin Routing Algorithm. 129-132
  
• Shuenn-Shi Chen, Jong-Jang Chen, Sao-Jie Chen, Chia-Chun Tsai:
  An Automatic Router for the Pin Grid Array Package. 133-136
  
• Tong Xiao, Malgorzata Marek-Sadowska:
  Crosstalk Reduction by Transistor Sizing. 137-140
  
• Wai-chee Wong, Philip C. H. Chan, Wai-on Law:
  A Technology-Independent Methodology of Placement Generation for Analog Circuit. 141-
  

DA for Electronic Packages

• Ching-Wei Yeh, Chin-Chao Chang, Jinn-Shyan Wang:
  Technnology Mapping for Low Power. 145-148
  
• Maolin Tang, Kamran Eshraghian, Hon Nin Cheung:
  An Efficient Aopproach to Constrained Via Minimization for Two-Layer VLSI Routing. 149-152
  
• Nagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri:
  Automatic Constraint Transformation with Integrated Parameter Space Exploration in Analog System Synthesis. 153-156
  
• Hoon Choi, Hansoo Kim, In-Cheol Park, Seung Ho Hwang, Chong-Min Kyung:
  Node Sampling Technique to Speed Up Probability-Based Power Estimation Methods. 157-160
  
• Hidehisa Nagano, Takayuki Suyama, Akira Nagoya:
  Acceleration of Linear Block Code Evaluations Using New Reconfigurable Computing Approach. 161-164
  
• Mark M. Gourary, Sergey G. Rusakov, Sergey L. Ulyanov, Michael M. Zharov, Brian J. Mulvaney:
  A New Numerical Method for Transient Noise Analysis of Nonlinear Circuits. 165-168
  
• Rung-Bin Lin, Jinq-Chang Chen:
  Low Power CMOS Off-Chip Drivers with Slew-rate Difference. 169-172
  
• Rung-Bin Lin, Isaac Shuo-Hsiu Chou, Chi-Ming Tsai:
  Benchmark Circuits Improve the Quality of a Standard Cell Library. 173-176
  
• Takashi Takenaka, Junji Kitamichi, Teruo Higashino, Kenichi Taniguchi:
  Formal Design Verification for Correctness of Pipelined Microprocessors with Out-of-order Instruction Execution. 177-180
  
• Koichi Hatta, Shin'ichi Wakabayashi, Tetsushi Koide:
  Solving the Rectangular Packing Problem by an Adaptive GA Based on Sequence-Pair. 181-184
  
• Ren-Der Chen, Jer-Min Jou, Yeu-Horng Shiau:
  Hazard-Free Synthesis and Decomposition of Asynchronous Circuits. 185-188
  
• Jiann-Horng Lin, Jing-Yang Jou, Iris Hui-Ru Jiang:
  Hierarchical Floorplan Design on the Internet. 189-192
  
• Ryoji Sakurai, Mizuki Takahashi, Andrew Kay, Akihisa Yamada, Tetsuya Fujimoto, Takashi Kambe:
  A Scheduling Method for Synchronous Communication in the Bach Hardware Compiler. 193-
  

Circuit 2 - Multmedia chip designs

• P. W. Cheng, H. C. Huang:
  Electronics Development of Silicon Microdisplay for Virtual Reality Applications. 197-200
  
• Seung-Min Lee, Jin-Hong Chung, Mike Myung-Ok Lee:
  High-Speed and Low-Power Real-Time Programmable Video Multi-Processor for MPEG-2 Multimedia Chip on 0.6µm TLM CMOS Technology. 201-204
  
• Jer-Min Jou, Pei-Yin Chen, Yeu-Horng Shiau, Ming-Shiang Liang:
  A Scalable Pipelined Architecture for Separable 2-D Discrete Wavelet Transform. 205-208
  
• Jer-Min Jou, Shiann-Rong Kuang, Yeu-Horng Shiau:
  A New Pipelined Architecture for Fuzzy Color Correction. 209-
  

Physical Design 5 - Special Topics

• Edoardo Charbon, Ilhami Torunoglu:
  Watermarking Layout Topologies. 213-216
  
• Youxin Gao, D. F. Wong:
  Optimal Wire Shape with Consideration of Coupling Capacitance under Elmore Delay Model. 217-220
  
• Andrew B. Kahng, Gabriel Robins, Anish Singh, Alexander Zelikovsky:
  New Multilevel and Hierarchical Algorithms for Layout Density Control. 221-224
  
• Ross Baldick, Andrew B. Kahng, Andrew A. Kennings, Igor L. Markov:
  Function Smoothing with Applications to VLSI Layout. 225-
  

Timing analysis

• Yun-Yin Lian, Youn-Long Lin:
  Layout-based Logic Decomposition for Timing Optimization. 229-232
  
• Chun-hong Chen, Chi-Ying Tsui:
  Timing Optimization of Logic Network Using Gate Duplication. 233-236
  
• Payam Rabiei, Massoud Pedram:
  Model Order Reduction of Large Circuits Using Balanced Truncation. 237-
  

Physical Design 6 - Placement & Route

• Andrew B. Kahng, Paul Tucker, Alexander Zelikovsky:
  Optimization of Linear Placements for Wirelength Minimization with Free Sites. 241-244
  
• Haiyun Bao, Xianlong Hong, Yici Cai:
  A New Global Routing Algorithm Independent Of Net Ordering. 245-248
  
• Gang Huang, Xianlong Hong, Changge Qiao, Yici Cai:
  A Timing-Driven Block Placer Based on Sequence Pair Model. 249-252
  
• Kenneth Y. Yun:
  Recent Advances in Asynchronous Design Methodologies. 253-
  

Circuit 3 - Analog & Mixed Circuit

• Jack L. Chan, Steve S. Chung:
  Universal Switched-Current Integrator Blocks for SI Filter Design. 261-264
  
• Lee Sung-Dae, Jang Myung-Jun, Leex Won-Hyo:
  An On-Chip Automatic Tuning Circuit using Integration Level Approximation. 265-268
  
• Won Hyo Lee, Jun Dong Cho, Sung Dae Lee:
  A High Speed and Low Power Phase-Frequency Detector and Charge - pump. 269-272
  
• Jin-Kug Lee, Dong-Young Chang, Geun-Soon Kang, Seung-Hoon Lee:
  A Single-Chip CMOS CCD Camera Interface Circuit with Digitally Controlled AGC. 273-
  

Testing 1

• Xiaowei Li, Paul Y. S. Cheung:
  Data Path Synthesis for BIST with Low Area Overhead. 275-278
  
• Chi-Feng Wu, Cheng-Wen Wu:
  Testing Interconnects of Dynamic Reconfigurable FPGAs. 279-282
  
• Yinlei Yu, Jian Xu, Wei-Kang Huang, Fabrizio Lombardi:
  Diagnosing Single Faults for Interconnects in SRAM Based FPGAs. 283-286
  
• Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattacharya:
  An Adaptive BIST to Detect Multiple Stuck-Open Faults in CMOS circuits. 287-
  

Power Estimation/Low-power

• Kai Zhang, Tsuyoshi Shinogi, Haruhiko Takase, Terumine Hayashi:
  A Method for Evaluating Upper Bound of Simultaneous Switching Gates Using Circuit Partition. 291-294
  
• Toshio Murayama, Kimihiro Ogawa, Haruhiko Yamaguchi:
  Estimation of Peak Current through CMOS VLSI Circuit Supply Lines. 295-298
  
• Yibin Ye, Kaushik Roy, Rolf Drechsler:
  Power Consumption in XOR-Based Circuits. 299-302
  
• Rolf Drechsler, Nicole Drechsler:
  Exploiting Don't Caers During Data Sequencing using Genetic Algorithms. 303-
  

Testing 2 - Testing and formal Verification

• Chun-Keung Lo, Philip C. H. Chan:
  An Efficient Structural Approach to Board Interconnect Diagnosis. 307-310
  
• Jin Ding, Yu-Liang Wu:
  On the Testing Quality of Random and Pseudo-random Sequences for Permanent and Intermittent Faults. 311-314
  
• Martin Keim, Nicole Drechsler, Bernd Becker:
  Combining GAs and Symbolic Methods for High Quality Tests of Sequential Circuits. 315-318
  
• Junji Kitamichi, Hiroyuki Kageyama, Nobuo Funabiki:
  Formal Verification Method for Combinatorial Circuits at High Level Design. 319-
  

BDD

• Wolfgang Günther, Rolf Drechsler:
  Minimization of Free BDDs. 323-326
  
• Christoph Meinel, Klaus Schwettmann, Anna Slobodová:
  Application Driven Variable Reordering and an Example Implementation in Reachability Analysis. 327-330
  
• Yukihiro Iguchi, Munehiro Matsuura, Tsutomu Sasao, Atsumu Iseno:
  Realization of Regular Ternary Logic Functions. 331-
  

Systems/HW SW co-design

• Nozomu Togawa, Takashi Sakurai, Masao Yanagisawa, Tatsuo Ohtsuki:
  A Hardware/Software Partitioning Algorithm for Processor Cores of Digital Signal Processing. 335-338
  
• Rainer Leupers, Johann Elste, Birger Landwehr:
  Generation of Interpretive and Compiled Instruction Set Simulators. 339-342
  
• Apostolos A. Kountouris, Christophe Wolinski:
  Combining Speculative Execution and Conditional Resource Sharing to Efficiently Schedule Conditional Behaviors. 343-346
  
• Marcello Lajolo, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli:
  Fast Instruction Cache Simulation Strategies in a Hardware/Software Co-Design Environment. 347-
  

Behavioral/FPGA

• Wen-Jong Fang, Peng-Cheng Kao, Allen C.-H. Wu:
  A Multi-Level FPGA Synthesis Method Supporting HDL Debugging for Emulation-Based Designs. 351-354
  
• Birger Landwehr:
  A Genetic Algorithm based Approach for Multi-Objective Data-Flow Graph Optimization. 355-358
  
• Debatosh Debnath, Tsutomu Sasao:
  Fast Boolean Matching Under Permutation Using Representative. 359-362
  
• Jinsong Bei, Hongxing Li, Jinian Bian, Hongxi Xue, Xianlong Hong:
  FSM Modeling of Synchronous VHDL Design for Symbolic Model Checking. 363-
  

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