ASP-DAC 2001: Yokohama, Japan
Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan. ACM 2001 ISBN 0-7803-6634-4- Kazutoshi Kobayashi, Makoto Eguchi, Takuya Iwahashi, Takehide Shibayama, Xiang Li, Kousuke Takai, Hidetoshi Onodera: A vector-pipeline DSP for low-rate videophones. 1-2
- Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada: A high-speed PLA using array logic circuits with latch sense amplifiers and a charge sharing scheme. 3-4
- Yasuo Arai: Multi-hit time-to-digital converter VLSI for high-energy physics experiments. 5-6
- Mitsuru Yamada, Akinori Nishihara: A high-speed FIR digital filter with CSD coefficients implemented on FPGA. 7-8
- Yong-Ha Park, Seon-Ho Han, Hoi-Jun Yoo: Single chip 3D rendering engine integrating embedded DRAM frame buffer and Hierarchical Octet Tree (HOT) array processor with bandwidth amplification. 9-10
- Yukio Mitsuyama, Zaldy Andales, Takao Onoye, Isao Shirakawa: A dynamically reconfigurable hardware-based cipher chip. 11-12
- Makoto Nagata, Takafumi Ohmoto, Jin Nagai, Takashi Morie, Atsushi Iwata: Test circuits for substrate noise evaluation in CMOS digital ICs. 13-14
- Roberto Y. Omaki, Yu Dong, Morgan Hirosuke Miki, Makoto Furuie, Daisuke Taki, Masaya Tarui, Gen Fujita, Takao Onoye, Isao Shirakawa: Realtime wavelet video coder based on reduced memory accessing. 15-16
- Daisuke Kawakami, Yuichiro Shibata, Hideharu Amano: A prototype chip of multicontext FPGA with DRAM for virtual hardware. 17-18
- Dongsheng Ma, Wing-Hung Ki, Chi-Ying Tsui, Philip K. T. Mok: A single-inductor dual-output integrated DC/DC boost converter for variable voltage scheduling. 19-20
- Tomohiro Nezuka, Masashi Hoshino, Makoto Ikeda, Kunihiro Asada: A smart position sensor for 3-D measurement. 21-22
- Toshiyuki Nozawa, Makoto Imai, Masanori Fujibayashi, Tadahiro Ohmi: A parallel vector quantization processor featuring an efficient search algorithm for real-time motion picture compression. 25-26
- Seokkee Kim, Jun-Ho Kwon, Soo-Ik Chae: An 8-b nRERL microprocessor for ultra-low-energy applications. 27-28
- Chung-Jr Lian, Liang-Gee Chen, Hao-Chieh Chang, Yung-Chi Chang: Design and implementation of JPEG encoder IP core. 29-30
- Kazuhiro Nakamura, Qiang Zhu, Shinji Maruoka, Takashi Horiyama, Shinji Kimura, Katsumasa Watanabe: A real-time 64-monosyllable recognition LSI with learning mechanism. 31-32
- Satoshi Sakaidani, Naoto Miyamoto, Tadahiro Ohmi: Flexible processor based on full-adder/ d-flip-flop merged module. 35-36
- Takanori Okuma, Koji Hashimoto, Kazuaki Murakami: Development of PPRAM-link interface (PLIF) IP core for high-speed inter-SoC communication. 37-38
- D. Miyawaki, Shizunori Matsumoto, Hans Jürgen Mattausch, S. Ooshiro, Masami Suetake, Michiko Miura-Mattausch, Shigetaka Kumashiro, Tetsuya Yamaguchi, Kyoji Yamashita, Noriaki Nakayama: Correlation method of circuit-performance and technology fluctuations for improved design reliability. 39-44
- Zhao Li, Xiao-Feng Xie, Wenjun Zhang, Zhilian Yang: Realization of semiconductor device synthesis with the parallel genetic algorithm. 45-49
- Martin R. Frerichs: Precise extraction of ultra deep submicron interconnect parasitics with parameterizable 3D-modeling: invited talk. 50-56
- Patrice Gerin, Sungjoo Yoo, Gabriela Nicolescu, Ahmed Amine Jerraya: Scalable and flexible cosimulation of SoC designs with heterogeneous multi-processor target architectures. 63-68
- Kjetil Svarstad, Nezih Ben-Fredj, Gabriela Nicolescu, Ahmed Amine Jerraya: A higher level system communication model for object-oriented specification and design of embedded systems. 69-77
- Chanik Park, Sungchan Kim, Soonhoi Ha: A dataflow specification for system level synthesis of 3D graphics applications. 78-84
- Christoph Scholl, Bernd Becker, Andreas Brogle: The multiple variable order problem for binary decision diagrams: theory and practical application. 85-90
- Wolfgang Günther, Andreas Hett, Bernd Becker: Application of linearly transformed BDDs in sequential verification. 91-96
- Christoph Meinel, Christian Stangier: A new partitioning scheme for improvement of image computation. 97-102
- Chien-Nan Jimmy Liu, I-Ling Chen, Jing-Yang Jou: An efficient design-for-verification technique for HDLs. 103-108
- Paul-Peter Sotiriadis, Anantha Chandrakasan: Reducing bus delay in submicron technology using coding. 109-114
- Yu-Min Lee, Hing Yin Lai, Charlie Chung-Ping Chen: Optimal spacing and capacitance padding for general clock structures. 115-119
- Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky: Provably good global buffering by multi-terminal multicommodity flow approximation. 120-125
- LiYi Lin, Yi-Yu Liu, TingTing Hwang: A construction of minimal delay Steiner tree using two-pole delay model. 126-132
- Andrew B. Kahng, Shailesh Vaya, Alexander Zelikovsky: New graph bipartizations for double-exposure, bright field alternating phase-shift mask layout. 133-138
- Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky: Hierarchical dummy fill for process uniformity. 139-144
- Sani R. Nassif: Modeling and forecasting of manufacturing variations (embedded tutorial). 145-150
- Takashi Kambe, Akihisa Yamada, Koichi Nishida, Kazuhisa Okada, Mitsuhisa Ohnishi, Andrew Kay, Paul Boca, Vince Zammit, Toshio Nomura: A C-based synthesis system, Bach, and its application (invited talk). 151-155
- Yuichiro Miyaoka, Yoshiharu Kataoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki: Area/delay estimation for digital signal processor cores. 156-161
- Peng-Cheng Kao, Chih-Kuang Hsieh, Allen C.-H. Wu: An RTL design-space exploration method for high-level applications. 162-168
- G. Subash Chandar, S. Vaideeswaran: Addressing verification bottlenecks of fully synthesized processor cores using equivalence checkers. 175-180
- Wanlin Cao, D. M. H. Walker, Rajarshi Mukherjee: An efficient solution to the storage correspondence problem for large sequential circuits. 181-186
- Hai Zhou, Narendra V. Shenoy, William Nicholls: Efficient minimum spanning tree construction without Delaunay triangulation. 192-197
- Payam Heydari, Massoud Pedram: Balanced truncation with spectral shaping for RLC interconnects. 203-208
- Mark M. Gourary, Sergey G. Rusakov, Sergey L. Ulyanov, Michael M. Zharov, Brian J. Mulvaney: An optimum fitting algorithm for generation of reduced-order models. 209-213
- Zhaozhi Yang, Zeyi Wang, Shuzhou Fang: A virtual 3-D multipole accelerated extractor for VLSI parasitic interconnect capacitance. 214-218
- Jian Qiao, Makoto Ikeda, Kunihiro Asada: Finding an optimal functional decomposition for LUT-based FPGA synthesis. 225-230
- Kenneth Yan: Practical logic synthesis for CPLDs and FPGAs with PLA-style logic blocks. 231-234
- Jae-Jin Kim, Hi-Seok Kim, Chi-Ho Lin: A new techology mapping for CPLD under the time constraint. 235-238
- Massoud Pedram: Power optimization and management in embedded systems. 239-244
- Wei-Chung Cheng, Massoud Pedram: Low power techniques for address encoding and memory allocation. 245-250
- Vishnu Swaminathan, Krishnendu Chakrabarty: Investigating the effect of voltage-switching on low-energy task scheduling in hard real-time systems. 251
- Joep L. W. Kessels, Ad M. G. Peeters: The tangram framework (embedded tutorial): asynchronous circuits for low power. 255-260
- Jeong-Gun Lee, Euiseok Kim, Dong-Ik Lee: Imprecise data computation for high performance asynchronous processors. 261-266
- Hidetoshi Onodera, Andrew B. Kahng, Wayne Wei-Ming Dai, Sani R. Nassif, Juho Kim, Akira Tanabe, Toshihiro Hattori: Beyond the red brick wall (panel): challenges and solutions in 50nm physical design. 267-268
- Kuniyuki Tani, Norihiro Nikai, Atsushi Wada, Tetsuro Sawai: A pipelined ADC macro design for multiple applications. 269-274
- Takeo Yasuda, Hiroaki Fujita, Hidetoshi Onodera: A dynamically phase adjusting PLL with a variable delay. 275-280
- Florin Balasa: Device-level placement for analog layout: an opportunity for non-slicing topological representations. 281-286
- Liyi Xiao, Bin Li, Yizheng Ye, Guoyong Huang, JinJun Guo, Peng Zhang: A mixed-signal simulator for VHDL-AMS. 287-292
- Shekhar Borkar: Low power design challenges for the decade (invited talk). 293-296
- Kazuhisa Sunaga, Tetsuo Endoh, Hiroshi Sakuraba, Fujio Masuoka: An on-chip 96.5% current efficiency CMOS linear regulator. 297-301
- Vasily G. Moshnyaga: Reducing cache engery through dual voltage supply. 302-305
- Tony Givargis, Frank Vahid, Jörg Henkel: Trace-driven system-level power evaluation of system-on-a-chip peripheral cores. 306-312
- Shi-Yu Huang: Towards the logic defect diagnosis for partial-scan designs. 313-318
- Biplab K. Sikdar, Debesh K. Das, Vamsi Boppana, Cliff Yang, Sobhan Mukherjee, Parimal Pal Chaudhuri: Cellular automata as a built in self test structure. 319-324
- Ching-Hong Tsai, Cheng-Wen Wu: Processor-programmable memory BIST for bus-connected embedded memories. 325-330
- Satoshi Ohtake, Shintaro Nagai, Hiroki Wada, Hideo Fujiwara: A DFT method for RTL circuits to achieve complete fault efficiency based on fixed-control testability. 331-334
- Chris J. Myers, Wendy Belluomini, Kip Kallpack, Eric Peskin, Hao Zheng: Timed circuits: a new paradigm for high-speed design. 335-340
- Bin Zhou, Tomohiro Yoneda, Bernd-Holger Schlingloff: Conformance and mirroring for timed asychronous circuits. 341-346
- Shuji Tsukiyama, Masakazu Tanaka, Masahiro Fukui: A statistical static timing analysis considering correlations between delays. 353-358
- Masanori Hashimoto, Hidetoshi Onodera: Post-layout transistor sizing for power reduction in cell-based design. 359-365
- Wenjian Yu, Zeyi Wang: An efficient quasi-multiple medium algorithm fo the capacitance extraction of actual 3-D VLSI interconnects. 366-372
- Jason Cong, David Zhigang Pan, Prasanna V. Srinivas: Improved crosstalk modeling for noise constrained interconnect optimization. 373-378
- Hao Ji, Anirudh Devgan, Wayne Wei-Ming Dai: KSim: a stable and efficient RKC simulator for capturing on-chip inductance effect. 379-384
- Chung-Hsien Wu, Jin-Hua Hong, Cheng-Wen Wu: RSA cryptosystem design based on the Chinese remainder theorem. 391-395
- Kazuhiro Nakamura, Qiang Zhu, Shinji Maruoka, Takashi Horiyama, Shinji Kimura, Katsumasa Watanabe: Speech recognition chip for monosyllables. 396-399
- Frank Gilbert, Alexander Worm, Norbert Wehn: Low power implementation of a turbo-decoder on programmable architectures. 400-403
- Hyeongseok Yu, Byung Wook Kim, Yeon Gon Cho, Jun-Dong Cho, Jea Woo Kim, Hyun Cheol Park, Ki Won Lee: Area-efficient and reusable VLSI architecture of decision feedback equalizer for QAM modern. 404-408
- Nikil D. Dutt, Alexandru Nicolau, Hiroyuki Tomiyama, Ashok Halambi: New directions in compiler technology for embedded systems (embedded tutorial). 409-414
- Markus Lorenz, David Koffmann, Steven Bashford, Rainer Leupers, Peter Marwedel: Optimized address assignment for DSPs with SIMD memory accesses. 415-420
- Partha S. Roop, Arcot Sowmya, S. Ramesh: A formal approach to component based development of synchronous programs. 421-424
- Hiroto Kagotani, Takuji Okamoto, Takashi Nanya: Synthesis of four-phase asynchronous control circuits from pipeline dependency graphs. 425-430
- Nattha Sretasereekul, Takashi Nanya: Eliminating isochronic-fork constraints in quasi-delay-insensitive circuits. 437-442
- Andrew B. Kahng: Design technology productivity in the DSM era (invited talk). 443-448
- Flavius Gruian, Krzysztof Kuchcinski: LEneS: task scheduling for low-energy systems using variable supply voltage processors. 449-455
- Tohru Ishihara, Kunihiro Asada: A system level memory power optimization technique using multiple supply and threshold voltages. 456-461
- Woo-Seung Yang, In-Cheol Park, Chong-Min Kyung: Low-power high-level synthesis using latches. 462-466
- José Alberto Espejo, Luis Entrena, Enrique San Millán, Emilio Olías: Functional extension of structural logic optimization techniques. 467-472
- Chin Ngai Sze, Yu-Liang Wu: Improved alternative wiring scheme applying dominator relationship. 473-478
- Andreas G. Veneris, Magdy S. Abadir, Ivor Ting: Design rewiring based on diagnosis techniques. 479-484
- Toshinori Hosokawa, Masayoshi Yoshimura, Mitsuyasu Ohta: Design for testability strategies using full/partial scan designs and test point insertions to reduce test application times. 485-491
- Chauchin Su, Shih-Ching Hsiao, Hau-Zen Zhau, Chung-Len Lee: A computer aided engineering system for memory BIST. 492-495
- Bhargab B. Bhattacharya, Alexej Dmitriev, Michael Gössel, Krishnendu Chakrabarty: Synthesis of single-output space compactors with application to scan-based IP cores. 496-502
- Yuchun Ma, Sheqin Dong, Xianlong Hong, Yici Cai, Chung-Kuan Cheng, Jun Gu: VLSI floorplanning with boundary constraints based on corner block list. 509-514
- Jianbang Lai, Ming-Shiun Lin, Ting-Chi Wang, Li-C. Wang: Module placement with boundary constraints using the sequence-pair representation. 515-520
- Xiaoping Tang, D. F. Wong: FAST-SP: a fast algorithm for block placement based on sequence pair. 521-526
- Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu, Dirk Stroobandt: Toward better wireload models in the presence of obstacles. 527-532
- Youxin Gao, D. F. Wong: A fast and accurate delay estimation method for buffered interconnects. 533-538
- Denis Deschacht, Grégory Servel: On-chip interconnections: impact of adjacent lines on timing. 539-544
- Seung-Ho Jung, Jong-Humn Baek, Seok-Yoon Kim: Short circuit power estimation of static CMOS circuits. 545-550
- Takahiro Murooka, Atsushi Takahara, Toshiaki Miyazaki: A novel network node architecture for high performance and function flexibility. 551-557
- Yajun Ha, Geert Vanmeerbeeck, Patrick Schaumont, Serge Vernalde, Marc Engels, Rudy Lauwereins, Hugo De Man: Virtual Java/FPGA interface for networked reconfiguration. 558-563
- Reiner W. Hartenstein: Coarse grain reconfigurable architecture (embedded tutorial). 564-570
- Rajeev Murgai: Efficient global fanout optimization algorithms. 571-576
- Ankur Srivastava, Chunhong Chen, Majid Sarrafzadeh: Timing driven gate duplication in technology independent phase. 577-582
- Shi-Yu Huang: On speeding up extended finite state machines using catalyst circuitry. 583-588
- I-Min Liu, Hung-Ming Chen, Tan-Li Chou, Adnan Aziz, D. F. Wong: Integrated power supply planning and floorplanning. 589-594
- Amir H. Ajami, Massoud Pedram: Post-layout timing-driven cell placement using an accurate net length model with movable Steiner points. 595-600
- Sheqin Dong, Xianlong Hong, Youliang Wu, Yizhou Lin, Jun Gu: VLSI block placement using less flexibility first principles. 601-604
- Wenting Hou, Hong Yu, Xianlong Hong, Yici Cai, Weimin Wu, Jun Gu, William H. Kao: A new congestion-driven placement algorithm based on cell inflation. 605-608
- Yumin Zhang, Xiaobo Sharon Hu, Danny Z. Chen: Cell selection from technology libraries for minimizing power. 609-614
- Per Lindgren, Mikael Kerttu, Mitchell A. Thornton, Rolf Drechsler: Low power optimization technique for BDD mapped circuits. 615-621
- Youngtae Kim, Taewhan Kim: Accurate exploration of timing and area trade-offs in arithmetic optimization using carry-save-adders. 622-628
- Elaheh Bozorgzadeh, Seda Ogrenci Memik, Majid Sarrafzadeh: RPack: routability-driven packing for cluster-based FPGAs. 629-634
- Zhi-Hong Wang, En-Cheng Liu, Jianbang Lai, Ting-Chi Wang: Power minization in LUT-based FPGA technology mapping. 635-640
- Hongbing Fan, Jiping Liu, Yu-Liang Wu: Combinatorial routing analysis and design of universal switch blocks. 641-644
- Malay Haldar, Anshuman Nayak, Alok N. Choudhary, Prithviraj Banerjee: Automated synthesis of pipelined designs on FPGAs for signal and image processing applications described in MATLAB. 645-648
- Akira Kitajima, Makiko Itoh, Jun Sato, Akichika Shiomi, Yoshinori Takeuchi, Masaharu Imai: Effectiveness of the ASIP design system PEAS-III in design of pipelined processors. 649-654
- Maria-Cristina V. Marinescu, Martin C. Rinard: High-level specification and efficient implementation of pipelined circuits. 655-661
- Jinhwan Jeon, Daehong Kim, Dongwan Shin, Kiyoung Choi: High-level synthesis under multi-cycle interconnect delay. 662
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last updated on 2013-06-19T203413 by the dblp team