ASP-DAC 2008:
Seoul,
Korea
Proceedings of the 13th Asia South Pacific Design Automation Conference, ASP-DAC 2008, Seoul, Korea, January 21-24, 2008.
IEEE 2008 BibTeX
- Jan M. Rabaey:
A brand new wireless day.
1
Electronic Edition (link) BibTeX
- Feng Wang, Xiaoxia Wu, Yuan Xie:
Variability-driven module selection with joint design time optimization and post-silicon tuning.
2-9
Electronic Edition (link) BibTeX
- Cheng-Tao Hsieh, Jason Cong, Zhiru Zhang, Shih-Chieh Chang:
Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA.
10-15
Electronic Edition (link) BibTeX
- Wei-Sheng Huang, Yu-Ru Hong, Juinn-Dar Huang, Ya-Shih Huang:
A multicycle communication architecture and synthesis flow for Global interconnect Resource Sharing.
16-21
Electronic Edition (link) BibTeX
- Wei Jiang, Zhiru Zhang, Miodrag Potkonjak, Jason Cong:
Scheduling with integer time budgeting for low-power optimization.
22-27
Electronic Edition (link) BibTeX
- Pushkar Tripathi, Rohan Jai, Srikanth Kurra, Preeti Ranjan Panda:
REWIRED - Register Write Inhibition by Resource Dedication.
28-31
Electronic Edition (link) BibTeX
- Tsuyoshi Sadakata, Yusuke Matsunaga:
An efficient performance improvement method utilizing specialized functional units in Behavioral Synthesis.
32-35
Electronic Edition (link) BibTeX
- Young-Si Hwang, Sung-Kwan Ku, Chan-Min Jung, Ki-Seok Chung:
Predictive power aware management for embedded mobile devices.
36-41
Electronic Edition (link) BibTeX
- Nikolaos D. Liveris, Hai Zhou, Prithviraj Banerjee:
A dynamic-programming algorithm for reducing the energy consumption of pipelined System-Level streaming applications.
42-48
Electronic Edition (link) BibTeX
- Ayse Kivilcim Coskun, Tajana Simunic Rosing, Keith Whisnant, Kenny C. Gross:
Temperature-aware MPSoC scheduling for reducing hot spots and gradients.
49-54
Electronic Edition (link) BibTeX
- Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Daihan Wang:
Run-time power gating of on-chip routers using look-ahead routing.
55-60
Electronic Edition (link) BibTeX
- Sushu Zhang, Karam S. Chatha:
Automated techniques for energy efficient scheduling on homogeneous and heterogeneous chip multi-processor architectures.
61-66
Electronic Edition (link) BibTeX
- Love Singhal, Sejong Oh, Eli Bozorgzadeh:
Statistical power profile correlation for realistic thermal estimation.
67-70
Electronic Edition (link) BibTeX
- Yexin Zheng, Chao Huang:
Reconfigurable RTD-based circuit elements of complete logic functionality.
71-76
Electronic Edition (link) BibTeX
- Somnath Paul, Swarup Bhunia:
MBARC: A scalable memory based reconfigurable computing framework for nanoscale devices.
77-82
Electronic Edition (link) BibTeX
- Mehdi Saeedi, Morteza Saheb Zamani, Mehdi Sedighi:
Moving forward: A non-search based synthesis method toward efficient CNOT-based quantum circuit synthesis algorithms.
83-88
Electronic Edition (link) BibTeX
- Rajesh Pande, Rajendra Patrikar:
A CAD tool for RF MEMS devices.
89-94
Electronic Edition (link) BibTeX
- Inhwa Jung, Moo-young Kim, Chulwoo Kim:
A 1.2GHz delayed clock generator for high-speed microprocessors.
95-96
Electronic Edition (link) BibTeX
- Akiko Mineyama, Hiroyuki Ito, Takahiro Ishii, Kenichi Okada, Kazuya Masu:
LVDS-type on-chip transmision line interconnect with passive equalizers in 90nm CMOS process.
97-98
Electronic Edition (link) BibTeX
- Young-Ho Kwak, Inhwa Jung, Chulwoo Kim:
A slew-rate controlled output driver with one-cycle tuning time.
99-100
Electronic Edition (link) BibTeX
- Tadayoshi Enomoto, Yuki Higuchi:
A low-leakage current power 180-nm CMOS SRAM.
101-102
Electronic Edition (link) BibTeX
- Hong Phuc Ninh, Takashi Moue, Takashi Kurashina, Kenichi Okada, Akira Matsuzawa:
A CMOS direct sampling mixer using Switched Capacitor Filter technique for software-defined radio.
103-104
Electronic Edition (link) BibTeX
- Susumu Sadoshima, Satoshi Fukuda, Tackya Yammouch, Hiroyuki Ito, Kenichi Okada, Kazuya Masu:
Small-area CMOS RF distributed mixer using multi-port inductors.
105-106
Electronic Edition (link) BibTeX
- Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye:
Dynamic supply noise measurement circuit composed of standard cells suitable for in-site SoC power integrity verification.
107-108
Electronic Edition (link) BibTeX
- Ji-Hoon Kim, In-Cheol Park:
Duo-binary circular turbo decoder based on border metric encoding for WiMAX.
109-110
Electronic Edition (link) BibTeX
- Tae-Hwan Kim, In-Cheol Park:
Area and power efficient design of coarse time synchronizer and frequency offset estimator for fixed WiMAX systems.
111-112
Electronic Edition (link) BibTeX
- Ronghua Lu, Jun Han, Xiaoyang Zeng, Qing Li, Lang Mai, Jia Zhao:
A low-cost cryptographic processor for security embedded system.
113-114
Electronic Edition (link) BibTeX
- Shih-Hao Ou, Tay-Jyi Lin, Xiang Sheng Deng, Zhi Hong Zhuo, Chih-Wei Liu:
Multithreaded coprocessor interface for multi-core multimedia SoC.
115-116
Electronic Edition (link) BibTeX
- Liang-Bi Chen, Yung-Chih Liu, Chen-Hung Chen, Chung-Fu Kao, Ing-Jer Huang:
Parameterized embedded in-circuit emulator and its retargetable debugging software for microprocessor/microcontroller/DSP processor.
117-118
Electronic Edition (link) BibTeX
- Yuen-Hong Alvin Ho, Chi-Un Lei, Hing-Kit Kwan, Ngai Wong:
Global optimization of common subexpressions for multiplierless synthesis of multiple constant multiplications.
119-124
Electronic Edition (link) BibTeX
- Tejaswi Gowda, Sarma B. K. Vrudhula:
Decomposition based approach for synthesis of multi-level threshold logic circuits.
125-130
Electronic Edition (link) BibTeX
- Yi Zhu, Jianhua Liu, Haikun Zhu, Chung-Kuan Cheng:
Timing-power optimization for mixed-radix Ling adders by integer linear programming.
131-137
Electronic Edition (link) BibTeX
- Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne:
Efficient synthesis of compressor trees on FPGAs.
138-143
Electronic Edition (link) BibTeX
- Taiga Takata, Yusuke Matsunaga:
Area recovery under depth constraint by Cut Substitution for technology mapping for LUT-based FPGAs.
144-147
Electronic Edition (link) BibTeX
- Sanghamitra Roy, Yu Hen Hu, Charlie Chung-Ping Chen, Shih-Pin Hung, Tse-Yu Chiang, Jiuan-Guei Tseng:
An optimal algorithm for sizing sequential circuits for industrial library based designs.
148-151
Electronic Edition (link) BibTeX
- Quan Chen, Ngai Wong:
Efficient numerical modeling of random rough surface effects for interconnect internal impedance extraction.
152-157
Electronic Edition (link) BibTeX
- Fang Gong, Wenjian Yu, Zeyi Wang, Zhiping Yu, Changhao Yan:
Efficient techniques for 3-D impedance extraction using mixed boundary element method.
158-163
Electronic Edition (link) BibTeX
- Yuichi Tanji, Takayuki Watanabe, Hideki Asai:
Generating stable and sparse reluctance/inductance matrix under insufficient conditions.
164-169
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- Duo Li, Sheldon X.-D. Tan:
Hierarchical Krylov subspace reduced order modeling of large RLC circuits.
170-175
Electronic Edition (link) BibTeX
- Yu Pu, Jose de Jesus Pineda de Gyvez, Henk Corporaal, Yajun Ha:
Statistical noise margin estimation for sub-threshold combinational circuits.
176-179
Electronic Edition (link) BibTeX
- Lihong Zhang, C.-J. Richard Shi, Yingtao Jiang:
Symmetry-aware placement with transitive closure graphs for analog layout design.
180-185
Electronic Edition (link) BibTeX
- Qing Dong, Shigetoshi Nakatake:
Constraint-free analog placement with topological symmetry structure.
186-191
Electronic Edition (link) BibTeX
- Tilen Ma, Evangeline F. Y. Young:
TCG-based multi-bend bus driven floorplanning.
192-197
Electronic Edition (link) BibTeX
- Chaomin Luo, Miguel F. Anjos, Anthony Vannelli:
Large-scale fixed-outline floorplanning design using convex optimization techniques.
198-203
Electronic Edition (link) BibTeX
- Dae Hyun Kim, Sung Kyu Lim:
Bus-aware microarchitectural floorplanning.
204-208
Electronic Edition (link) BibTeX
- Xin Li, Yuchun Ma, Xianlong Hong, Sheqin Dong, Jason Cong:
LP based white space redistribution for thermal via planning and performance optimization in 3D ICs.
209-212
Electronic Edition (link) BibTeX
- Nishath Verghese, Richard Rouse, Philippe Hurat:
Predictive models and CAD methodology for pattern dependent variability.
213-218
Electronic Edition (link) BibTeX
- Sani R. Nassif:
Technology modeling and characterization beyond the 45nm node.
219
Electronic Edition (link) BibTeX
- David Z. Pan, Minsik Cho:
Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond.
220-225
Electronic Edition (link) BibTeX
- Michael D. Moffitt:
MaizeRouter: Engineering an effective global router.
226-231
Electronic Edition (link) BibTeX
- Jhih-Rong Gao, Pei-Ci Wu, Ting-Chi Wang:
A new global router for modern designs.
232-237
Electronic Edition (link) BibTeX
- Yoichi Tomioka, Atsushi Takahashi:
Routability driven modification method of monotonic via assignment for 2-layer Ball Grid Array packages.
238-243
Electronic Edition (link) BibTeX
- Lijuan Luo, Martin D. F. Wong:
Ordered escape routing based on Boolean satisfiability.
244-249
Electronic Edition (link) BibTeX
- Anand Rajaram, David Z. Pan:
MeshWorks: An efficient framework for planning, synthesis and optimization of clock mesh networks.
250-257
Electronic Edition (link) BibTeX
- Luca P. Carloni, Andrew B. Kahng, Swamy Muddu, Alessandro Pinto, Kambiz Samadi, Puneet Sharma:
Interconnect modeling for improved system-level design optimization.
258-264
Electronic Edition (link) BibTeX
- Jeremy Chan, Sri Parameswaran:
NoCOUT : NoC topology generation with mixed packet-switched and point-to-point networks.
265-270
Electronic Edition (link) BibTeX
- Gunar Schirner, Andreas Gerstlauer, Rainer Dömer:
Automatic generation of hardware dependent software for MPSoCs from abstract system specifications.
271-276
Electronic Edition (link) BibTeX
- Shan Yan, Bill Lin:
Application-specific Network-on-Chip architecture synthesis based on set partitions and Steiner Trees.
277-282
Electronic Edition (link) BibTeX
- Hoonmo Yang:
Floating-point reconfiguration array processor for 3D graphics physics engine.
283
Electronic Edition (link) BibTeX
- Xu Cheng:
Super-K: A SoC for single-chip ultra mobile computer.
284
Electronic Edition (link) BibTeX
- Ki-Soo Hwang:
The evolution of SoC platform according to the new mobile paradigm.
285
Electronic Edition (link) BibTeX
- Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera:
Statistical gate delay model for Multiple Input Switching.
286-291
Electronic Edition (link) BibTeX
- Katsumi Homma, Izumi Nitta, Toshiyuki Shibuya:
Non-Gaussian Statistical Timing models of die-to-die and within-die parameter variations for full chip analysis.
292-297
Electronic Edition (link) BibTeX
- Leronq Cheng, Jinjun Xiong, Lei He:
Non-Gaussian statistical timing analysis using second-order polynomial fitting.
298-303
Electronic Edition (link) BibTeX
- Saihua Lin, Yu Wang, Rong Luo, Huazhong Yang:
A capacitive boosted buffer technique for high-speed process-variation-tolerant interconnect in UDVS application.
304-309
Electronic Edition (link) BibTeX
- Ruiming Chen, Lizheng Zhang, Vladimir Zolotov, Chandu Visweswariah, Jinjun Xiong:
Static timing: Back to our roots.
310-315
Electronic Edition (link) BibTeX
- Jui-Yuan Hsieh, Shanq-Jang Ruan:
Synthesis and design of parameter extractors for low-power pre-computation-based content-addressable memory using gate-block selection algorithm.
316-321
Electronic Edition (link) BibTeX
- Dominic Hillenbrand, Jörg Henkel:
Block cache for embedded systems.
322-327
Electronic Edition (link) BibTeX
- Aviral Shrivastava, Ilya Issenin, Nikil Dutt:
A Compiler-in-the-Loop framework to explore Horizontally Partitioned Cache architectures.
328-333
Electronic Edition (link) BibTeX
- Ajay K. Verma, Philip Brisk, Paolo Ienne:
Fast, quasi-optimal, and pipelined instruction-set extensions.
334-339
Electronic Edition (link) BibTeX
- Mei Wen, Nan Wu, Maolin Guan, Chunyuan Zhang:
Load scheduling: Reducing pressure on distributed register files for free.
340-345
Electronic Edition (link) BibTeX
- Tao Luo, David Z. Pan:
DPlace2.0: A stable and efficient analytical placement based on diffusion.
346-351
Electronic Edition (link) BibTeX
- Tao Luo, David Newmark, David Z. Pan:
Total power optimization combining placement, sizing and multi-Vt through slack distribution management.
352-357
Electronic Edition (link) BibTeX
- Yongqiang Lu, Qing Su, Jamil Kawa:
An innovative Steiner tree based approach for polygon partitioning.
358-363
Electronic Edition (link) BibTeX
- Ming-Chao Tsai, Yung-Chia Lin, Ting-Chi Wang:
An MILP-based wire spreading algorithm for PSM-aware layout modification.
364-369
Electronic Edition (link) BibTeX
- Yanfeng Wang, Qiang Zhou, Yici Cai, Jiang Hu, Xianlong Hong, Jinian Bian:
Low power clock buffer planning methodology in F-D placement for large scale circuit design.
370-375
Electronic Edition (link) BibTeX
- Sani R. Nassif:
Power grid analysis benchmarks.
376-381
Electronic Edition (link) BibTeX
- Junehee Lee:
In-band mobile digital TV transmission technology for advanced television systems committee.
382
Electronic Edition (link) BibTeX
- Shorin Kyo, Shin'ichiro Okazaki:
In-vehicle vision processors for driver assistance systems.
383-388
Electronic Edition (link) BibTeX
- Doug Pulley:
Multi-core DSP for base stations: Large and small.
389-391
Electronic Edition (link) BibTeX
- Tatsuo Nakagawa, Masayuki Miyazaki, Goichi Ono, Ryosuke Fujiwara, Takayasu Norimatsu, Takahide Terada, Akira Maeki, Yuji Ogata, Shinsuke Kobayashi, Noboru Koshizuka, Ken Sakamura:
1-cc computer using UWB-IR for wireless sensor network.
392-397
Electronic Edition (link) BibTeX
- Udo Krautz, Markus Wedler, Wolfgang Kunz, Kai Weber, Christian Jacobi, Matthias Pflanz:
Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proof.
398-403
Electronic Edition (link) BibTeX
- Alexander Jesser, Lars Hedrich:
A symbolic approach for mixed-signal model checking.
404-409
Electronic Edition (link) BibTeX
- Chao Yan, Mark R. Greenstreet:
Faster projection based methods for circuit level verification.
410-415
Electronic Edition (link) BibTeX
- Shan Tang, Qiang Xu:
A debug probe for concurrently debugging multiple embedded cores and inter-core transactions in NoC-based systems.
416-421
Electronic Edition (link) BibTeX
- Kyuho Shim, Youngrae Cho, Namdo Kim, Hyuncheol Baik, Kyungkuk Kim, Dusung Kim, Jaebum Kim, Byeongun Min, Kyumyung Choi, Maciej J. Ciesielski, Seiyang Yang:
A fast two-pass HDL simulation with on-demand dump.
422-427
Electronic Edition (link) BibTeX
- Li-Pin Chang:
Hybrid solid-state disks: Combining heterogeneous NAND flash in large SSDs.
428-433
Electronic Edition (link) BibTeX
- Alexandros Bartzas, Miguel Peon-Quiros, Stylianos Mamagkakis, Francky Catthoor, Dimitrios Soudris, Jose Manuel Mendias:
Enabling run-time memory data transfer optimizations at the system level with automated extraction of embedded software metadata information.
434-439
Electronic Edition (link) BibTeX
- Pramod Chandraiah, Rainer Dömer:
Automatic re-coding of reference code into structured and analyzable SoC models.
440-445
Electronic Edition (link) BibTeX
- Hassan Ghasemzadeh, Eric Guenterberg, Katherine Gilani, Roozbeh Jafari:
Action coverage formulation for power optimization in body sensor networks.
446-451
Electronic Edition (link) BibTeX
- Heng Yu, Bharadwaj Veeravalli, Yajun Ha:
Dynamic scheduling of imprecise-computation tasks in maximizing QoS under energy constraints for embedded systems.
452-455
Electronic Edition (link) BibTeX
- Duo Li, Sheldon X.-D. Tan, Murli Tirumala:
Architecture-level thermal behavioral characterization for multi-core microprocessors.
456-461
Electronic Edition (link) BibTeX
- Pei-Yu Huang, Chih-Kang Lin, Yu-Min Lee:
Full-chip thermal analysis for the early design stage via generalized integral transforms.
462-467
Electronic Edition (link) BibTeX
- Hwisung Jung, Massoud Pedram:
A stochastic local hot spot alerting technique.
468-473
Electronic Edition (link) BibTeX
- Anupama R. Subramaniam, Ritu Singhal, Chi-Chao Wang, Yu Cao:
Design rule optimization of regular layout for leakage reduction in nanoscale design.
474-479
Electronic Edition (link) BibTeX
- Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Saumil Shah, Dennis Sylvester:
Investigation of diffusion rounding for post-lithography analysis.
480-485
Electronic Edition (link) BibTeX
- Debasish Das, Kip Killpack, Chandramouli V. Kashyap, Abhijit Jas, Hai Zhou:
Pessimism reduction in coupling-aware static timing analysis using timing and logic filtering.
486-491
Electronic Edition (link) BibTeX
- Kui Wang, Hao Fang, Hu Xu, Xu Cheng:
A fast incremental clock skew scheduling algorithm for slack optimization.
492-497
Electronic Edition (link) BibTeX
- Matthew R. Guthaus, Dennis Sylvester, Richard B. Brown:
Clock tree synthesis with data-path sensitivity matching.
498-503
Electronic Edition (link) BibTeX
- Jacob R. Minz, Xin Zhao, Sung Kyu Lim:
Buffered clock tree synthesis for 3D ICs under thermal variations.
504-509
Electronic Edition (link) BibTeX
- Guofei Zhou, Li Su, Depeng Jin, Lieguang Zeng:
A delay model for interconnect trees based on ABCD matrix.
510-513
Electronic Edition (link) BibTeX
- Rajeshwary Tayade, Sani R. Nassif, Jacob Abraham:
Analytical model for the impact of multiple input switching noise on timing.
514-517
Electronic Edition (link) BibTeX
- Takashi Sato, Hiroyuki Ueyama, Noriaki Nakayama, Kazuya Masu:
Determination of optimal polynomial regression function to decompose on-die systematic and random variations.
518-523
Electronic Edition (link) BibTeX
- Brendan Hargreaves, Henrik Hult, Sherief Reda:
Within-die process variations: How accurately can they be statistically modeled?
524-530
Electronic Edition (link) BibTeX
- Jin Sun, Yue Huang, Jun Li, Janet Meiling Wang:
Chebyshev Affine Arithmetic based parametric yield prediction under limited descriptions of uncertainty.
531-536
Electronic Edition (link) BibTeX
- Markus Olbrich, Erich Barke:
Distribution arithmetic for stochastical analysis.
537-542
Electronic Edition (link) BibTeX
- Sridhar Varadan, Janet Meiling Wang, Jiang Hu:
Handling partial correlations in yield prediction.
543-548
Electronic Edition (link) BibTeX
- David Atienza, Giovanni De Micheli, Luca Benini, José L. Ayala, Pablo Garcia Del Valle, Michael DeBole, Vijay Narayanan:
Reliability-aware design for nanometer-scale devices.
549-554
Electronic Edition (link) BibTeX
- Soo-Kwan Eo, Sungjoo Yoo, Kyu-Myung Choi:
An industrial perspective of power-aware reliable SoC design.
555-557
Electronic Edition (link) BibTeX
- F. C. Tseng:
The future of semiconductor industry - A foundry's perspective.
558
Electronic Edition (link) BibTeX
- Kai-Chiang Wu, Diana Marculescu:
Soft error rate reduction using redundancy addition and removal.
559-564
Electronic Edition (link) BibTeX
- Yu Hu, Xiang Fu, Xiaoxin Fan, Hideo Fujiwara:
Localized random access scan: Towards low area and routing overhead.
565-570
Electronic Edition (link) BibTeX
- Fei Wang, Yu Hu, Huawei Li, Xiaowei Li:
A design- for-diagnosis technique for diagnosing both scan chain faults and combinational circuit faults.
571-576
Electronic Edition (link) BibTeX
- Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
GECOM: Test data compression combined with all unknown response masking.
577-582
Electronic Edition (link) BibTeX
- Minje Jun, Sungjoo Yoo, Eui-Young Chung:
Mixed integer linear programming-based optimal topology synthesis of cascaded crossbar switches.
583-588
Electronic Edition (link) BibTeX
- ChangRyul Yun, DongSoo Kang, YoungHwan Bae, Hanhn Cho, KyoungSon Jhang:
Automatic interface synthesis based on the classification of interface protocols of IPs.
589-594
Electronic Edition (link) BibTeX
- Carlo Curino, Luca Fossati, Vincenzo Rana, F. Redaelli, Marco D. Santambrogio, Donatella Sciuto:
The Shining embedded system design methodology based on self dynamic reconfigurable architectures.
595-600
Electronic Edition (link) BibTeX
- Sujan Pandey, Rolf Drechsler:
Robust on-chip bus architecture synthesis for MPSoCs under random tasks arrival.
601-606
Electronic Edition (link) BibTeX
- Jung-Ho Lee, Sung-Rok Yoon, Kwang-Eui Pyun, Sin-Chong Park:
A Multi-Processor NoC platform applied on the 802.11i TKIP cryptosystem.
607-610
Electronic Edition (link) BibTeX
- Michael B. Healy, Fayez Mohamood, Hsien-Hsin S. Lee, Sung Kyu Lim:
A unified methodology for power supply noise reduction in modern microarchitecture design.
611-616
Electronic Edition (link) BibTeX
- Xiaoyi Wang, Jin Shi, Yici Cai, Xianlong Hong:
Heuristic power/ground network and floorplan co-design method.
617-622
Electronic Edition (link) BibTeX
- Shuai Li, Jin Shi, Yici Cai, Xianlong Hong:
Vertical via design techniques for multi-layered P/G networks.
623-628
Electronic Edition (link) BibTeX
- Jinseob Jeong, Seungwhun Paik, Youngsoo Shin:
Statistical mixed Vt allocation of body-biased circuits for reduced leakage variation.
629-634
Electronic Edition (link) BibTeX
- Swaroop Ghosh, Kaushik Roy:
Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching.
635-640
Electronic Edition (link) BibTeX
- Irith Pomeranz, Sudhakar M. Reddy:
Circuit lines for guiding the generation of random test sequences for synchronous sequential circuits.
641-646
Electronic Edition (link) BibTeX
- Sunghoon Chun, Taejin Kim, Sungho Kang:
A new low energy BIST using a statistical code.
647-652
Electronic Edition (link) BibTeX
- Jia Li, Qiang Xu, Yu Hu, Xiaowei Li:
On reducing both shift and capture power for scan-based testing.
653-658
Electronic Edition (link) BibTeX
- Xiang Fu, Huawei Li, Yu Hu, Xiaowei Li:
Robust test generation for power supply noise induced path delay faults.
659-662
Electronic Edition (link) BibTeX
- Irith Pomeranz, Sudhakar M. Reddy:
Test vector chains for increased targeted and untargeted fault coverage.
663-666
Electronic Edition (link) BibTeX
- Raimund Ubar, Sergei Devadze, Jaan Raik, Artur Jutman:
Parallel fault backtracing for calculation of fault coverage.
667-672
Electronic Edition (link) BibTeX
- Giovanni Beltrame, Cristiana Bolchini, Luca Fossati, Antonio Miele, Donatella Sciuto:
ReSP: A non-intrusive Transaction-Level Reflective MPSoC Simulation Platform for design space exploration.
673-678
Electronic Edition (link) BibTeX
- Dawei Wang, Sikun Li, Yong Dou:
Collaborative hardware/software partition of coarse-grained reconfigurable system using evolutionary ant colony optimization.
679-684
Electronic Edition (link) BibTeX
- Farhad Mehdipour, Hamid Noori, Morteza Saheb Zamani, Koji Inoue, Kazuaki Murakami:
Design space exploration for a coarse grain accelerator.
685-690
Electronic Edition (link) BibTeX
- Martin Lukasiewycz, Michael Glaß, Christian Haubelt, Jürgen Teich:
Efficient symbolic multi-objective design space exploration.
691-696
Electronic Edition (link) BibTeX
- Kazuyuki Tanimura, Ryuta Nara, Shunitsu Kohara, Kazunori Shimizu, Youhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
Scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2n).
697-702
Electronic Edition (link) BibTeX
- ByungHyun Lee, Taewhan Kim:
Optimal allocation and placement of thermal sensors for reconfigurable systems and its practical extension.
703-707
Electronic Edition (link) BibTeX
- Reinaldo A. Bergamaschi, Guoling Han, Alper Buyuktosunoglu, Hiren D. Patel, Indira Nair, Gero Dittmann, Geert Janssen, Nagu R. Dhanwada, Zhigang Hu, Pradip Bose, John A. Darringer:
Exploring power management in multi-core systems.
708-713
Electronic Edition (link) BibTeX
- Toshinori Sato, Toshimasa Funaki:
Dependability, power, and performance trade-off on a multicore processor.
714-719
Electronic Edition (link) BibTeX
- Ling Zhang, Jianhua Liu, Haikun Zhu, Chung-Kuan Cheng, Masanori Hashimoto:
High performance current-mode differential logic.
720-725
Electronic Edition (link) BibTeX
- Kunhyuk Kang, Saakshi Gangwal, Sang Phill Park, Kaushik Roy:
NBTI induced performance degradation in logic and memory circuits: how effectively can we approach a reliability solution?
726-731
Electronic Edition (link) BibTeX
- J. S. Hobbs, T. W. Williams:
Reaching the limits of low power design.
732-735
Electronic Edition (link) BibTeX
- Hiroaki Shikano, Masaki Ito, Kunio Uchiyama, Toshihiko Odaka, Akihiro Hayashi, Takeshi Masuura, Masayoshi Mase, Jun Shirako, Yasutaka Wada, Keiji Kimura, Hironori Kasahara:
Software-cooperative power-efficient heterogeneous multi-core for media processing.
736-741
Electronic Edition (link) BibTeX
- Shi-Hao Chen, Jiing-Yuan Lin:
Experiences of low power design implementation and verification.
742-747
Electronic Edition (link) BibTeX
- Shuichi Kunie, Takefumi Hiraga, Tatsuya Tokue, Sunao Torii, Taku Ohsawa:
Low power architecture and design techniques for mobile handset LSI MedityTM M2.
748-753
Electronic Edition (link) BibTeX
- Chenjie Gu, Jaijeet S. Roychowdhury:
An efficient, fully nonlinear, variability-aware non-monte-carlo yield estimation procedure with applications to SRAM cells and ring oscillators.
754-761
Electronic Edition (link) BibTeX
- Darius Grabowski, Markus Olbrich, Erich Barke:
Analog circuit simulation using range arithmetics.
762-767
Electronic Edition (link) BibTeX
- Tuck Boon Chan, Hsin-Chia Lu, Jun-Kuei Zeng, Charlie Chung-Ping Chen:
LTCC spiral inductor modeling, synthesis, and optimization.
768-771
Electronic Edition (link) BibTeX
- Jiayi Liu, Sheqin Dong, Xianlong Hong, Yibo Wang, Ou He, Satoshi Goto:
Symmetry constraint based on mismatch analysis for analog layout in SOI technology.
772-775
Electronic Edition (link) BibTeX
- Jonghee W. Yoon, Aviral Shrivastava, Sanghyun Park, Minwook Ahn, Reiley Jeyapaul, Yunheung Paek:
SPKM : A novel graph drawing based algorithm for application mapping onto coarse-grained reconfigurable architectures.
776-782
Electronic Edition (link) BibTeX
- Mohammed Abid Hussain, Madhu Mutyam:
Block remap with turnoff: A variation-tolerant cache design technique.
783-788
Electronic Edition (link) BibTeX
- Sudeep Pasricha, Nikil Dutt:
ORB: An on-chip optical ring bus communication architecture for multi-processor systems-on-chip.
789-794
Electronic Edition (link) BibTeX
- Marc Somers, JoAnn M. Paul:
Webpage-based benchmarks for mobile device design.
795-800
Electronic Edition (link) BibTeX
- Grant Martin:
Panel: Best ways to use billions of devices on a chip.
801-802
Electronic Edition (link) BibTeX
- Shoaib Akram, Scott Cromar, Gregory Lucas, Alexandros Papakonstantinou, Deming Chen:
VEBoC: Variation and error-aware design for billions of devices on a chip.
803-808
Electronic Edition (link) BibTeX
- Nikil Dutt:
Quo vadis, BTSoC (Billion Transistor SoC)?
809
Electronic Edition (link) BibTeX
- KyungHo Kim:
Best ways to use billions of devices on a wireless mobile SoC.
810
Electronic Edition (link) BibTeX
- Kazutoshi Kobayashi, Hidetoshi Onodera:
Best ways to use billions of devices on a chip - Error predictive, defect tolerant and error recovery designs.
811-812
Electronic Edition (link) BibTeX
Copyright © Wed Jul 23 15:57:26 2008
by Michael Ley (ley@uni-trier.de)
