Taipei, Taiwan Proceedings of the 15th Asia South Pacific Design Automation Conference, ASP-DAC 2010, Taipei, Taiwan, January 18-21, 2010.
IEEE 2010, ISBN 978-1-60558-837-7
Embedded systems design techniques
Advanced model order reduction technique
techniques for efficient energy harvesting and generation for portable and embedded systems
Memory management and compiler techniques
- Yi He, Chun Jason Xue, Cathy Qun Xu, Edwin Hsing-Mean Sha:
Co-optimization of memory access and task scheduling on MPSoC architectures with multi-level memory.
- Hiroaki Tanaka, Yutaka Ota, Nobu Matsumoto, Takuji Hieda, Yoshinori Takeuchi, Masaharu Imai:
A new compilation technique for SIMD code generation across basic block boundaries.
- Wei-Tsun Sun, Zoran Salcic, Avinash Malik:
LibGALS: a library for GALS systems design and modeling.
- Tiantian Liu, Minming Li, Chun Jason Xue:
Joint variable partitioning and bank selection instruction optimization on embedded systems with multiple memory banks.
Power and signal integrity
- Wanping Zhang, Ling Zhang, Amirali Shayan Arani, Wenjian Yu, Xiang Hu, Zhi Zhu, A. Ege Engin, Chung-Kuan Cheng:
On-chip power network optimization with decoupling capacitors and controlled-ESRs.
- Xiang Hu, Wenbo Zhao, Peng Du, Amirali Shayan Arani, Chung-Kuan Cheng:
An adaptive parallel flow for power distribution network simulation using discrete Fourier transform.
- Yongho Lee, Taewhan Kim:
Technique for controlling power-mode transition noise in distributed sleep transistor network.
- Shuichi Aono, Masaki Unno, Hideki Asai:
A novel FDTD algorithm based on alternating-direction explicit method with PML absorbing boundary condition.
3D integration and networks on chips
Emerging memories and 3D ICs
- Paul Falkenstern, Yuan Xie, Yao-Wen Chang, Yu Wang:
Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis.
- Xin Zhao, Sung Kyu Lim:
Power and slew-aware clock network design for through-silicon-via (TSV) based 3D ICs.
- J. Singh, Krishnan Ramakrishnan, S. Mookerjea, Suman Datta, Narayanan Vijaykrishnan, D. K. Pradhan:
A novel si-tunnel FET based SRAM design for ultra low-power 0.3V VDD applications.
- Chang-Tzu Lin, Ding-Ming Kwai, Yung-Fa Chou, Ting-Sheng Chen, Wen Ching Wu:
CAD reference flow for 3D via-last integrated circuits.
- Dimin Niu, Yibo Chen, Xiangyu Dong, Yuan Xie:
Energy and performance driven circuit design for emerging phase-change memory.
Macromodeling and verification of analog systems
System-level modelling and analysis
recent advancement in post-silicon validation
New techniques for beyond-die routing
Analog layout and testing
- Zheng Liu, Lihong Zhang:
A performance-constrained template-based layout retargeting algorithm for analog integrated circuits.
- Rui He, Lihong Zhang:
Symmetry-aware TCG-based placement design under complex multi-group constraints for analog circuit layouts.
- Shigetoshi Nakatake, Masahiro Kawakita, Takao Ito, Masahiro Kojima, Michiko Kojima, Kenji Izumi, Tadayuki Habasaki:
Regularity-oriented analog placement with diffusion sharing and well island generation.
- Ji Hwan (Paul) Chun, Jae Wook Lee, Jacob A. Abraham:
A novel characterization technique for high speed I/O mixed signal circuit components using random jitter injection.
New techniques in technology mapping
- Fang-Yu Fan, Hung-Ming Chen, I-Min Liu:
Technology mapping with crosstalk noise avoidance.
- Ju-Yueh Lee, Yu Hu, Rupak Majumdar, Lei He, Minming Li:
Fault-tolerant resynthesis with dual-output LUTs.
- Kuan-Hsien Ho, Jie-Hong R. Jiang, Yao-Wen Chang:
TRECO: dynamic technology remapping for timing engineering change orders.
- Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga:
Multi-operand adder synthesis on FPGAs using generalized parallel counters.
University LSI design contest
- Yoshiaki Tashiro, Shun Kawada, Shin Sakai, Shigetoshi Sugawa:
Checker-pattern and shared two pixels LOFIC CMOS image sensors.
- Takahiro Kohara, Woonghee Lee, Koichi Mizobuchi, Shigetoshi Sugawa:
A CMOS image sensor with 2.0-e- random noise and 110-ke- full well capacity using column source follower readout circuits.
- Shun Kawada, Shin Sakai, Yoshiaki Tashiro, Shigetoshi Sugawa:
Checkered white-RGB color LOFIC CMOS image sensor.
- Risako Takashima, Yuya Hanai, Yuichi Hori, Tadahiro Kuroda:
A versatile recognition processor for sensor network applications.
- Daisuke Imanishi, Jee Young Hong, Kenichi Okada, Akira Matsuzawa:
A 2-6 GHz fully integrated tunable CMOS power amplifier for multi-standard transmitters.
- Liang-Bi Chen, Tsung-Yu Ho, Jiun-Cheng Ju, Cheng-Lung Chiang, Chung-Nan Lee, Ing-Jer Huang:
An embedded debugging/performance monitoring engine for a tile-based 3D graphics SoC development.
- Shingo Mandai, Toru Nakura, Makoto Ikeda, Kunihiro Asada:
Cascaded time difference amplifier using differential logic delay cell.
- Chen-I Chung, Jyun-Sian Jhou, Ching-Hwa Cheng:
Built-in self at-speed delay binning and calibration mechanism in wireless test platform.
- Elone Lee, Feng-Tso Chien, Ching-Hwa Cheng, Jiun-In Guo:
Dynamic voltage domain assignment technique for low power performance manageable cell based design.
- Hiroshi Fuketa, Masanori Hashimoto, Yukio Mitsuyama, Takao Onoye:
Adaptive performance control with embedded timing error predictive sensors for subthreshold circuits.
- Naoki Takayama, Kota Matsushita, Shogo Ito, Ning Li, Kenichi Okada, Akira Matsuzawa:
A 60GHz direct-conversion transmitter in 65nm CMOS technology.
- Hiroyuki Morimoto, Hiroki Koike, Kazuyuki Nakamura:
An electrically adjustable 3-terminal regulator with post-fabrication level-trimming function.
- Chen-I Chung, Shuo-Wen Chang, Feng-Tso Chien, Ching-Hwa Cheng:
Fine resolution double edge clipping with calibration technique for built-in at-speed delay testing.
- Daisuke Ikebuchi, Naomi Seki, Yu Kojima, M. Kamata, Lei Zhao, Hideharu Amano, Toshiaki Shirai, Satoshi Koyama, Tatsunori Hashida, Y. Umahashi, Hiroki Masuda, Kimiyoshi Usami, Seidai Takeda, Hiroshi Nakamura, Mitaro Namiki, Masaaki Kondo:
Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gating.
- Hiroaki Arai, Naoto Miyamoto, Koji Kotani, Hisanori Fujisawa, Takashi Ito:
A WiMAX turbo decoder with tailbiting BIP architecture.
- Naoto Miyamoto, Tadahiro Ohmi:
Temporal circuit partitioning for a 90nm CMOS multi-context FPGA and its delay measurement.
- Masa-Aki Fukase, Ryosuke Murakami, Tomoaki Sato:
Design and chip implementation of an instruction scheduling free ubiquitous processor.
- Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Masayuki Kimura, Hideharu Amano:
MuCCRA-3: a low power dynamically reconfigurable processor array.
- Steve C. L. Yuen, Yanqing Ai, Brian P. W. Chan, Thomas C. P. Chau, Sam M. H. Ho, Oscar K. L. Lau, Kong-Pang Pun, Philip Heng Wai Leong, Oliver C. S. Choy:
Rapid prototyping on a structured ASIC fabric.
- Jian-Lung Tzeng, Chien-Jen Huang, Yu-Han Yuan, Hsi-Pin Ma:
A high performance low complexity joint transceiver for closed-loop MIMO applications.
Clock network analysis and optimization
Test solutions for emerging applications
Power, performance and reliability in SoC design
- Aditya Yanamandra, Soumya Eachempati, Niranjan Soundararajan, Vijaykrishnan Narayanan, Mary Jane Irwin, Ramakrishnan Krishnan:
Optimizing power and performance for reliable on-chip networks.
- Wei Song, Doug Edwards:
A low latency wormhole router for asynchronous on-chip networks.
- Tsung-Yi Wu, Tzi-Wei Kao, Shi-Yi Huang, Tai-Lun Li, How-Rern Lin:
Combined use of rising and falling edge triggered clocks for peak current reduction in IP-based SoC designs.
- Jin Sun, Roman L. Lysecky, Karthik Shankar, Avinash Karanth Kodi, Ahmed Louri, Janet Meiling Wang:
Workload capacity considering NBTI degradation in multi-core systems.
Advances in modern clock tree routing
Timing-related testing and diagnosis
- Meng-Fan Wu, Hsin-Cheih Pan, T.-H. Wang, Jiun-Lang Huang, Kun-Han Tsai, Wu-Tung Cheng:
Improved weight assignment for logic switching activity during at-speed test pattern generation.
- Zijian He, Tao Lv, Huawei Li, Xiaowei Li:
Graph partition based path selection for testing of small delay defects.
- Irith Pomeranz, Sudhakar M. Reddy:
Functional and partially-functional skewed-load tests.
- Ke Peng, Yu Huang, Ruifeng Guo, Wu-Tung Cheng, Mohammad Tehranipoor:
Emulating and diagnosing IR-drop by using dynamic SDF.
Application-specific NoC design
Is 3D integration an opportunity or just a hype?
- Jin-Fu Li, Cheng-Wen Wu:
Is 3D integration an opportunity or just a hype?
- Kyu-Myung Choi:
An industrial perspective of 3D IC integration technology: from the viewpoint of design technology.
- Ding-Ming Kwai:
Homogeneous integration for 3D IC with TSV.
Modern floorplanning and placement techniques
Power optimization and estimation in the DSM Era
- Jungsoo Kim, Younghoon Lee, Sungjoo Yoo, Chong-Min Kyung:
An analytical dynamic scaling of supply voltage and body bias exploiting memory stall time variation.
- Jun Seomun, Seungwhun Paik, Youngsoo Shin:
Bounded potential slack: enabling time budgeting for dual-Vt allocation of hierarchical design.
- Quang Dinh, Deming Chen, Martin D. F. Wong:
Dynamic power estimation for deep submicron circuits with process variation.
- Dongkeun Oh, Nam Sung Kim, Charlie Chung-Ping Chen, Azadeh Davoodi, Yu Hen Hu:
Runtime temperature-based power estimation for optimizing throughput of thermal-constrained multi-core processors.
Design verification and debugging
Dependable silicon design with unreliable components
- James Tschanz, Keith A. Bowman, Muhammad M. Khellah, Chris Wilkerson, Bibiche M. Geuskens, Dinesh Somasekhar, Arijit Raychowdhury, Jaydeep Kulkarni, Carlos Tokunaga, Shih-Lien Lu, Tanay Karnik, Vivek De:
Resilient design in scaled CMOS for energy efficiency.
- Siva Narendra:
Benefits and barriers for probabilistic design.
- Lakshmi N. Chakrapani, Krishna V. Palem:
A probabilistic Boolean logic for energy efficient circuit and system design.
Patterning and physical design
- Jae-Seok Yang, Katrina Lu, Minsik Cho, Kun Yuan, David Z. Pan:
A new graph-theoretic, multi-objective layout decomposition framework for double patterning lithography.
- Jinyu Zhang, Wei Xiong, Yan Wang, Zhiping Yu, Min-Chun Tsai:
A robust pixel-based RET optimization algorithm independent of initial conditions.
- Kuen-Yu Tsai, Wei-Jhih Hsieh, Yuan-Ching Lu, Bo-Sen Chang, Sheng-Wei Chien, Yi-Chang Lu:
A new method to improve accuracy of parasitics extraction considering sub-wavelength lithography effects.
- Chih-Ta Lin, Yen-Hung Lin, Guan-Chan Su, Yih-Lang Li:
Dead via minimization by simultaneous routing and redundant via insertion.
Design and verification for process variation issues
New advances in high-level synthesis
- Yibo Chen, Yuan Xie, Yu Wang, Andrés Takach:
Minimizing leakage power in aging-bounded high-level synthesis with design time multi-Vth assignment.
- Taemin Kim, Xun Liu:
A global interconnect reduction technique during high level synthesis.
- Luciano Lavagno, Alex Kondratyev, Yosinori Watanabe, Qiang Zhu, Mototsugu Fujii, Mitsuru Tatesawa, Noriyasu Nakayama:
Incremental high-level synthesis.
- Nagaraju Pothineni, Philip Brisk, Paolo Ienne, Anshul Kumar, Kolin Paul:
A high-level synthesis flow for custom instruction set extensions for application-specific processors.
analysis and synthesis of multi-core systems
Power grid analysis
- Baktash Boghrati, Sachin S. Sapatnekar:
Incremental solution of power grids using random walks.
- Duo Li, Sheldon X.-D. Tan, Ning Mi, Yici Cai:
Efficient power grid integrity analysis using on-the-fly error check and reduction.
- Li Li, Yuchun Ma, Ning Xu, Yu Wang, Xianlong Hong:
PS-FPG: pattern selection based co-design of floorplan and power/ground network with wiring resource optimization.
- Takaaki Okumura, Fumihiro Minami, Kenji Shimazaki, Kimihiko Kuwada, Masanori Hashimoto:
Gate delay estimation in STA under dynamic power supply noise.
High-level synthesis and optimization for performance and power
ESL, the road to glory, or is it not? Real stories about using ESL design methodology in product development
- Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, John Sartori:
Slack redistribution for graceful degradation under voltage overscaling.
- Hassan Ebrahimi, Morteza Saheb Zamani, Hamid R. Zarandi:
A decoder-based switch box to mitigate soft errors in SRAM-based FPGAs.
- Hongbo Zhang, Martin D. F. Wong, Kai-Yuan Chao:
On process-aware 1-D standard cell design.
- Bo Liu, Toru Fujimura, Bo Yang, Shigetoshi Nakatake:
D-A converter based variation analysis for analog layout design.
Emerging circuits and architectures
System-level MPSoC analysis and optimization
Embedded software development for multi-processor systems-on-chip
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