ASPLOS-IV, 1991: Santa Clara, California

David A. Patterson (Ed.): ASPLOS-IV Proceedings - Forth International Conference on Architectural Support for Programming Languages and Operating Systems, Santa Clara, California, USA, April 8-11, 1991. ACM Press 1991, ISBN 0-89791-380-9

SIGARCH Computer Architecture News 19(2), SIGOPS Operating System Review 25(Special Issue April 1991), and SIGPLAN Notices 26(4)

Multiple Instructions Per Cycle Machines

Andrew Wolfe, John Paul Shen:
A Variable Instruction Stream Extension to the VLIW Architecture. 2-14
Manolis Katevenis, Nestoras Tzartzanis:
Reducing the Branch Penalty by Rearranging Instructions in Double-Width Memory. 15-27
Roland L. Lee, Alex Y. Kwok, Faye A. Briggs:
The Floating-Point Performance of a Superscalar SPARC Processor. 28-37

Cache Conscious Designs

David Callahan, Ken Kennedy, Allan Porterfield:
Software Prefetching. 40-52
Gurindar S. Sohi, Manoj Franklin:
High-Bandwidth Data Memory Systems for Superscalar Processors. 53-62
Monica S. Lam, Edward E. Rothberg, Michael E. Wolf:
The Cache Performance and Optimizations of Blocked Algorithms. 63-74
Jeffrey C. Mogul, Anita Borg:
The Effect of Context Switches on Cache Performance. 75-84

Architectural Support For Operating Systems

David Keppel:
A Portable Interface for On-the-Fly Instruction Space Modifiction. 86-95
Andrew W. Appel, Kai Li:
Virtual Memory Primitives for User Programs. 96-107
Thomas E. Anderson, Henry M. Levy, Brian N. Bershad, Edward D. Lazowska:
The Interaction of Architecture and Operating System Design. 108-120

Architectural Support For Programming Languages

David G. Bradlee, Susan J. Eggers, Robert R. Henry:
Integrating Register Allocation and Instruction Scheduling for RISCs. 122-131
Manuel E. Benitez, Jack W. Davidson:
Code Generation for Streaming: An Access/Execute Mechanism. 132-141
Rajive Bagrodia, Sharad Mathur:
Efficient Implementation of High Level Parallel Programs. 142-151

Instruction-Level Parallelism

William H. Mangione-Smith, Santosh G. Abraham, Edward S. Davidson:
Vector Register Design for Polycyclic Vector Scheduling. 154-163
David E. Culler, Anurag Sah, Klaus E. Schauser, Thorsten von Eicken, John Wawrzynek:
Fine-Grain Parallelism with Minimal Hardware Support: A Compiler-Controlled Threaded Abstract Machine. 164-175
David W. Wall:
Limits of Instruction-Level Parallelism. 176-188

I/O and Operating Systems

Edward K. Lee, Randy H. Katz:
Performance Consequences of Parity Placement in Disk Arrays. 190-199
Vincent Cate, Thomas R. Gross:
Integration of Compression and Caching for a Two-Level File System. 200-211
William J. Bolosky, Michael L. Scott, Robert P. Fitzgerald, Robert J. Fowler, Alan L. Cox:
NUMA Policies and Their Relation to Memory Architecture. 212-221

Architectural Support For Multiprocessors

David Chaiken, John Kubiatowicz, Anant Agarwal:
LimitLESS Directories: A Scalable Cache Coherence Scheme. 224-234
Sang Lyul Min, Jong-Deok Choi:
An Efficient Cache-Based Access Anomaly Detection Scheme. 235-244
Kourosh Gharachorloo, Anoop Gupta, John L. Hennessy:
Performance Evaluation of Memory Consistency Models for Shared Memory Multiprocessors. 245-257

Multiprocessors and Memory Management

Eric Freudenthal, Allan Gottlieb:
Process Coordination with Fetch-and-Increment. 260-268
John M. Mellor-Crummey, Michael L. Scott:
Synchronization without Contention. 269-278
Douglas Johnson:
The Case for a Read Barrier. 279-287

Quantitative Analysis of RISCs

Robert F. Cmelik, Shing I. Kong, David R. Ditzel, Edmund J. Kelly:
An Analysis of SPARC and MIPS Instruction Set Utilization on the SPEC Benchmarks. 290-302
C. Brian Hall, Kevin O'Brien:
Performance Characteristics of Architectural Features of the IBM RISC System/6000. 303-309
Dileep Bhandarkar, Douglas W. Clark:
Performance From Architecture: Comparing a RISC and CISC with Similar Hardware Organization. 310-319

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