8. ASYNC 2002: Manchester, UK

8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 9-11 April 2002, Manchester, UK. IEEE Computer Society 2002, ISBN 0-7695-1540-1

High-Speed and Energy-Efficient Pipelines

Hans M. Jacobson, Prabhakar Kudva, Pradip Bose, Peter W. Cook, Stanley Schuster:
Synchronous Interlocked Pipelines. 3-12
Recep O. Ozdag, Peter A. Beerel:
High-Speed QDI Asynchronous Pipelines. 13-22
Rajit Manohar, Clinton Kelly IV, John Teifel, David Fang, David Biermann:
Energy-Efficient Pipelines. 23-33

Novel Self-Timed Circuit Experiments

Mark R. Greenstreet, Brian D. Winters:
A Negative-Overhead, Self-Timed Pipeline. 37-46
Mark R. Greenstreet, Anthony Winstanley, Aurélien Garivier:
An Event Spacing Experiment. 47-56

Mixed Synchronous/Asynchronous Communication and Design

Joep L. W. Kessels, Suk-Jin Kim, Ad M. G. Peeters, Paul Wielage:
Clock Synchronization through Handshake Signalling. 59-68
George S. Taylor, Simon W. Moore, Robert D. Mullins, Peter Robinson:
Point to Point GALS Interconnect. 69-75
Eckhard Grass, Bodhisatya Sarker, Koushik Maharatna:
A Dual-Mode Synchronous/Asynchronous CORDIC Processor. 76-83
José A. Tierno, Sergey Rylov, Alexander Rylyakov, Montek Singh, Steven M. Nowick:
An Adaptively-Pipelined Mixed Synchronous-Asynchronous Digital FIR Filter Chip Operating at 1.3 GigaHertz. 84-95

Timing Analysis and Verification

Rohan Angrish, Supratik Chakraborty:
Probabilistic Timing Analysis of Asynchronous Systems with Moments of Delay. 99-108
Metehan Özcan, Masashi Imai, Takashi Nanya:
Generation and Verification of Timing Constraints for Fine-Grain Pipelined Asynchronous Data-Path Circuits. 109-114
Peter A. Beerel, Ken S. Stevens, Hoshik Kim:
Relative Timing Based Verification of Timed Circuits and Systems. 115-124

High-Level Design and Analysis of Self-Timed Circuits - Luciano Lavagno

Alexandre V. Bystrov, Alexandre Yakovlev:
Asynchronous Circuit Synthesis by Direct Mapping: Interfacing to Environment. 127-136
Rudolf H. Mak:
Design and Performance Analysis of Buffers: A Constructive Approach. 137-148
Alex Kondratyev, Oriol Roig, Lawrence Neukom, Karl Fant, Alexander Taubin:
Checking Delay-Insensitivity: 10⁴ Gates and Beyond. 149-157

Production Testing - Chair: Marly Roncken

Frank te Beest, Kees van Berkel, Ad M. G. Peeters:
Adding Synchronous and LSSD Modes to Asynchronous Circuits. 161-170
Amy Streich, Alex Kondratyev, Lief Sorensen:
Testing of Asynchronous Designs by "Inappropriate" Means: Synchronous Approach. 171-180
Thomas Villiger, Stephan Oetiker, Frank K. Gürkaynak, Norbert Felber, Hubert Kaeslin, Wolfgang Fichtner:
A Functional Test Methodology for Globally-Asynchronous Locally-Synchronous Systems. 181-189
D. J. Kinniment, Oleh V. Maevsky, Gordon Russell, Alexandre Yakovlev, Alexandre V. Bystrov:
On-Chip Structures for Timing Measurements and Test. 190-197

Security

W. J. Bainbridge, Andrew Bardsley, Steve Temple, Jim D. Garside, P. A. Riocreux, Luis A. Plana:
SPA - A Synthesisable Amulet Core for Smartcard pplications. 201-210
Simon W. Moore, Robert D. Mullins, Paul A. Cunningham, Ross J. Anderson, George S. Taylor:
Improving Smart Card Security Using Self-Timed Circuits. 211-218

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