9. ASYNC 2003: Vancouver, BC, Canada

9th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), 12-16 May 2003, Vancouver, BC, Canada. IEEE Computer Society 2003, ISBN 0-7695-1898-2

Asynchronous Processors

Robert B. Reese, Mitchell A. Thornton, Cherrice Traver:
A Coarse-Grain Phased Logic CPU. 2-13
Alain J. Martin, Mika Nyström, Karl Papadantonakis, Paul I. Pénzes, Piyush Prakash, Catherine G. Wong, Jonathan Chang, Kevin S. Ko, Benjamin Lee, Elaine Ou, James Pugh, Eino-Ville Talvala, James T. Tong, Ahmet Tura:
The Lutonium: A Sub-Nanojoule Asynchronous 8051 Microcontroller. 14-23
Clinton Kelly IV, Virantha N. Ekanayake, Rajit Manohar:
SNAP: A Sensor-Network Asynchronous Processor. 24-35

Pipeline Design and Tools

William S. Coates, Robert J. Drost:
Congestion and Starvation Detection in Ripple FIFOs. 36-45
Aristides Efthymiou, Jim D. Garside:
Adaptive Pipeline Structures fo Speculation Control. 46-55
Kenneth S. Stevens:
Energy and Performance Models for Clocked and Asynchronous Communication. 56-67

Synchronization

Yaron Semiat, Ran Ginosar:
Timing Measurements of Synchronization Circuits. 68-77
Ajanta Chakraborty, Mark R. Greenstreet:
Efficient Self-Timed Interfaces for Crossing Clock Domains. 78-88
Ran Ginosar:
Fourteen Ways to Fool Your Synchronizer. 89-97

Asynchronous Circuit Analysis

Nikolai Starodoubtsev, Sergei Bystrov, Alexandre Yakovlev:
Monotonic Circuits with Complete Acknowledgement. 98-108
Steven M. Nowick, Charles W. O'Donnell:
On the Existence of Hazard-Free Multi-Level Logic. 109-120
Mark B. Josephs:
An Analysis of Determinacy Using a Trace-Theoretic Model of Asynchronous Circuits. 121-131

Interconnect Methods

W. J. Bainbridge, W. B. Toms, David A. Edwards, Stephen B. Furber:
Delay-Insensitive, Point-to-Point Interconnect Using M-of-N Codes. 132-140
Thomas Villiger, Hubert Kaeslin, Frank K. Gürkaynak, Stephan Oetiker, Wolfgang Fichtner:
Self-Timed Ring for Globally-Asynchronous Locally-Synchronous Systems. 141-150
John Teifel, Rajit Manohar:
A High-Speed Clockless Serial Link Transceiver. 151-163

Synthesis

Alexandre V. Bystrov, Danil Sokolov, Alexandre Yakovlev:
Low-Latency Contro Structures with Slack. 164-173
Virantha N. Ekanayake, Rajit Manohar:
Asynchronous DRAM Design and Synthesis. 174-183
Hiroshi Saito, Euiseok Kim, Nattha Sretasereekul, Masashi Imai, Hiroshi Nakamura, Takashi Nanya:
Control Signal Sharing Using Data-Path Delay Information at Control Data Flow Graph Descriptions. 184-195

Power Management in Security and Signal Processing

Emmanuel Allier, Gilles Sicard, Laurent Fesquet, Marc Renaudin:
A New Class of Asynchronous A/D Converters Based on Time Quantization. 196-205
Z. C. Yu, Stephen B. Furber, Luis A. Plana:
An Investigation into the Security of Self-Timed Circuits. 206-215
Yee William Li, George Patounakis, Anup Jose, Kenneth L. Shepard, Steven M. Nowick:
Asynchronous Datapath with Software-Controlled On-Chip Adaptive Voltage Scaling for Multirate Signal Processing Application. 216-226

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