10. ASYNC 2004: Crete, Greece

@proceedings{DBLP:conf/async/2004,
  title     = {10th International Symposium on Advanced Research in Asynchronous
               Circuits and Systems (ASYNC 2004), 19-23 April 2004, Crete, Greece},
  booktitle = {ASYNC},
  publisher = {IEEE Computer Society},
  year      = {2004},
  isbn      = {0-7695-2133-9},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

Keynote I

• Christer Svensson:
  Synchronous Latency Insensitive Design. 3
  

Design and Test

• Jo C. Ebergen, Daniel Finchelstein, Russell Kao, Jon K. Lexau, David Hopkins:
  A Fast and Energy-Efficient Stack. 7-16
  
• John Teifel, Rajit Manohar:
  Static Tokens: Using Dataflow to Automate Concurrent Pipeline Synthesis. 17-27
  
• Radu Negulescu:
  General Testers for Asynchronous Circuits. 28-38
  

Timing

• Scott Fairbanks, Simon W. Moore:
  Analog Micropipeline Rings for High Precision Timing. 41-50
  
• Jo C. Ebergen, Jonathan Gainsley, Paul Cunningham:
  Transistor Sizing: How to Control the Speed and Energy Consumption of a Circuit. 51-61
  
• Masashi Imai, Metehan Özcan, Takashi Nanya:
  Evaluation of Delay Variation in Asynchronous Circuits Based on the Scalable-Delay-Insensitive Model. 62-71
  

Asynchronous Designs I

• David Fang, Rajit Manohar:
  Non-Uniform Access Asynchronous Register Files. 75-85
  
• Alireza Kaviani:
  Phase Alignment Using Asynchronous State Machines. 86-94
  
• Marcos Ferretti, Recep O. Ozdag, Peter A. Beerel:
  High Performance Asynchronous ASIC Back-End Design Flow Using Single-Track Full-Buffer Standard Cells. 95-105
  

Keynote I

• Martin Jenkner:
  Contacting Biological Cells with Electronic Circuits. 109
  

Synthesis and Verification

• Xiaohua Kong, Radu Negulescu:
  Bolstering Faith in GasP Circuits through Formal Verification. 113-124
  
• Mathew A. Sacker, Andrew D. Brown, Peter R. Wilson, Andrew J. Rushton:
  A General Purpose Behavioural Asynchronous Synthesis System. 125-134
  
• Tomohiro Yoneda, Hiroomi Onda, Chris J. Myers:
  Synthesis of Speed Independent Circuits Based on Decomposition. 135-145
  

Synchronization

• Ivan Blunno, Jordi Cortadella, Alex Kondratyev, Luciano Lavagno, Kelvin Lwin, Christos P. Sotiriou:
  Handshake Protocols for De-Synchronization. 149-158
  
• Greg Semeraro, David H. Albonesi, Grigorios Magklis, Michael L. Scott, Steven G. Dropsho, Sandhya Dwarkadas:
  Hiding Synchronization Delays in a GALS Processor Microarchitecture. 159-169
  
• Rostislav (Reuven) Dobkin, Ran Ginosar, Christos P. Sotiriou:
  Data Synchronization Issues in GALS SoCs. 170-180
  

Keynote III

• Ad M. G. Peeters:
  Bringing Handshake Technology to the Open Market. 183
  

Asynchronous Design II

• Recep O. Ozdag, Peter A. Beerel:
  A Channel Based Asynchronous Low Power High Performance Standard-Cell Based Sequential Decoder Implemented with QDI Templates. 187-197
  
• F. Aeschlimann, Emmanuel Allier, Laurent Fesquet, Marc Renaudin:
  Asynchronous FIR Filters: Towards a New Digital Processing Chain. 198-206
  
• Aristides Efthymiou, W. Suntiamorntut, Jim D. Garside, L. E. M. Brackenbury:
  An Asynchronous, Iterative Implementation of the Original Booth Multiplication Algorithm. 207-215
  

High Speed and Pulse Logic

• Nisrine Saadallah, Xiaohua Kong, Radu Negulescu:
  High-Speed Reduced Stack Dual Lock Circuits. 219-228
  
• Mika Nyström, Elaine Ou, Alain J. Martin:
  An Eight-Bit Divider Implemented in Asynchronous Pulse Logic. 229-239
  
• Ron Ho, Jonathan Gainsley, Robert J. Drost:
  Long Wires and Asynchronous Control. 240-249