5. Asian Test Symposium 1996: Hsinchu, Taiwan

Keynote Speech

• Sudhakar M. Reddy:
  "Challenges in Testing". 2-
  

Test Pattern Generation

• Vishwani D. Agrawal, Michael L. Bushnell, Qing Lin:
  Redundancy Identification Using Transitive Closure. 4-9
  
• Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen:
  Invalid State Identification for Sequential Circuit Test Generation. 10-15
  
• Irith Pomeranz, Sudhakar M. Reddy:
  On Test Generation for Interconnected Finite-State Machines: The Input Sequence Propagation Problem. 16-21
  
• Dirk Stroobandt, Jan Van Campenhout:
  Hierarchical Test Generation with Built-In Fault Diagnosis. 22-28
  
• J. Th. van der Linden, M. H. Konijnenburg, A. J. van de Goor:
  Circuit Partitioned Automatic Test Pattern Generation Constrained by Three-State Buses and Restrictors. 29-33
  
• Michael Nicolaidis, Rubin A. Parekhji, M. Boudjit:
  E-Groups: A New Technique for Fast Backward Propagation in System Level Test Generation. 34-41
  
• Y.-M. Hur, J.-H. Shin, K.-H. Lee, Y.-S. Son, I.-C. Lim, Y.-H. Kim:
  Efficient Path Delay Fault Test Generation Algorithms for Weighted Random Robust Testing. 42-
  

Board and System-Level Test

• Wuudiann Ke:
  Hybrid Pin Control Using Boundary-Scan And Its Applications. 44-49
  
• Jin-Hua Hong, Chung-Hung Tsai, Cheng-Wen Wu:
  Hierarchical Testing Using the IEEE Std 1149.5 Module Test and Maintenance Slave Interface Module. 50-55
  
• Po-Ching Hsu, Sying-Jyan Wang:
  Testing And Diagnosis Of Board Interconnects In Microprocessor-Based Systems. 56-61
  
• Chauchin Su, Shyh-Shen Hwang, Shyh-Jye Jou, Yuan-Tzu Ting:
  Syndrome Simulation And Syndrome Test For Unscanned Interconnects. 62-67
  
• Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Tomoo Inoue, Hideo Fujiwara:
  A Test Methodology for Interconnect Structures of LUT-based FPGAs. 68-74
  
• Wang-Dauh Tseng, Kuochen Wang:
  Testable Design and Testing of MCMs Based on Multifrequency Scan. 75-
  

Design for Testability

• Yoshihiro Konno, Kazushi Nakamura, Tatsushige Bitoh, Koji Saga, Seiken Yano:
  A Consistent Scan Design System for Large-Scale ASICs. 82-87
  
• Toshinori Hosokawa, Kenichi Kawaguchi, Mitsuyasu Ohta, Michiaki Muraoka:
  A Design for testability Method Using RTL Partitioning. 88-93
  
• Yoshinobu Higami, Seiji Kajihara, Kozo Kinoshita:
  Partially Parallel Scan Chain for Test Length Reduction by Using Retiming Technique. 94-99
  
• Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang, Cheng-Liang Tsai:
  Combination Of Automatic Test Pattern Generation And Built-In Intermediate Voltage Sensing For Detecting CMOS Bridging Faults. 100-
  

Concurrent Error Detection and Fault Tolerance

• Naotake Kamiura, Yutaka Hata, Kazuharu Yamato:
  On Design of Fail-Safe Cellular Arrays. 107-112
  
• Yoon-Hwa Choi, Pong-Gyou Lee:
  Concurrent Error Detection and Fault Location in a Fast ATM Switch. 113-118
  
• Kazuo Kawakubo, Koji Tanaka, Hiromi Hiraishi:
  Formal Verification Of Self-Testing Properties Of Combinational Circuits. 119-122
  
• Yupin Luo, Shiyuan Yang, Dongcheng Hu:
  Constructing an Edge-Route Guaranteed Optimal Fault-Tolerant Routing for Biconnected Graphs. 123-
  

Synthesis for Testability

• Tomoo Inoue, Toshimitsu Masuzawa, Hiroshi Youra, Hideo Fujiwara:
  An Approach To The Synthesis Of Synchronizable Finite State Machines With Partial Scan. 130-135
  
• Zhuxing Zhao, Zhongcheng Li, Yinghua Min:
  Waveform Polynomial Manipulation Using Bdds. 136-141
  
• Li-Ren Huang, Jing-Yang Jou, Sy-Yen Kuo, Wen-Bin Liao:
  Easily Testable Data Path Allocation Using Input/Output Registers. 142-
  
• Harry Hengster, Rolf Drechsler, Bernd Becker, Stefan Eckrich, Tonja Pfeiffer:
  AND/EXOR based Synthesis of Testable KFDD-Circuits with Small Depth. 148-
  
• Uwe Sparmann, H. Mueller, Sudhakar M. Reddy:
  Minimal Delay Test Sets for Unate Gate Networks. 155-
  

IDDQ and Fault Modeling

• Kuen-Jong Lee, Jing-Jou Tang:
  Two Modeling Techniques For CMOS Circuits To Enhance Test Generation And Fault Simulation For Bridging Faults. 165-171
  
• Toshimasa Kuchii, Masaki Hashizume, Takeomi Tamesada:
  Algorithmic Test Generation for Supply Current Testing of TTL Combinational Circuits. 171-176
  
• Hisashi Kondo, Kwang-Ting Cheng:
  An Efficient Compact Test Generator for IDDQ Testing. 177-182
  
• A. J. van de Goor, Georgi Gaydadjiev:
  Realistic Linked Memory Cell Array Faults. 183-188
  
• Teruhiko Yamada, Tsuyoshi Sasaki:
  On Current Testing of Josephson Logic Circuits Using the 4JL Gate Family. 189-
  

Keynote Speech

• Kwang-Ting Cheng:
  Built-In Self Test for Analog and Mixed-Signal Designs. 197-198
  
• Li-Ren Huang, Jing-Yang Jou, Sy-Yen Kuo:
  An Efficient PRPG Strategy By Utilizing Essential Faults. 199-204
  
• Saman Adham, Sanjay Gupta:
  DP-BIST: A Built-In Self Test For DSP DataPaths A Low Overhead and High Fault Coverage Technique. 205-212
  
• Bin-Hong Lin, Shao-Hui Shieh, Cheng-Wen Wu:
  A MISR Computation Algorithm for Fast Signature Simulation. 213-218
  
• Kowen Lai, Christos A. Papachristou:
  BIST Testability Enhancement of System Level Circuits : Experience with An Industrial Design. 219-
  

Circuit and System-Level Diagnostics

• Irith Pomeranz, Sudhakar M. Reddy:
  Low-Complexity Fault Diagnosis Under the Multiple Observation Time Testing Approach. 226-231
  
• Tao Wei, Mike W. T. Wong, Y. S. Lee:
  Efficient Multifrequency Analysis of Fault Diagnosis in Analog Circuits Based on Large Change Sensitivity Computation. 232-237
  
• Yuan-Tzu Ting, Li Wei Chao, Wei Chung Chao:
  A Practical Implementation Of Dynamic Testing Of An Ad Converter. 238-243
  
• Christopher P. Fuhrman, Henri J. Nussbaumer:
  Comparison Diagnosis in Large Multiprocessor Systems. 244-
  

Industrial Applications

• Najmi T. Jarwala, Paul W. Rutkowski, Shianling Wu, Chi W. Yau:
  Lessons Learned from Practical Applications of BIST/B-S Technology. 251-257
  
• Jwu E. Chen:
  Yield Improvement by Test Error Cancellation. 258-262
  
• Vladimir Castro Alves, A. Ribeiro Antunes, Meryem Marzouki:
  A Pragmatic, Systematic And Flexible Synthesis For Testability Methodology. 263-268
  
• Daisuke Teratani, Yoshiaki Kakuda, Tohru Kikuno:
  A New Model with Time Constraints for Conformance Testing of Communication Protocols. 269-
  

Practical Issues

• Cheng-Ping Wang, Chin-Long Wey:
  Test Generation Of Analog Switched-Current Circuits. 276-281
  
• Vladimir Székely, Márta Rencz, Jean-Michel Karam, Marcelo Lubaszewski, Bernard Courtois:
  Thermal Monitoring Of Safety-Critical Integrated Systems. 282-288
  
• Xiaofan Yang, Tinghuai Chen, Zehan Cao, Zhongshi He, Hongqing Cao:
  A New Scheme For The Fault Diagnosis Of Multiprocessor Systems. 289-294
  
• Serge N. Demidenko, Vincenzo Piuri:
  On-Line Testing In Digital Neural Networks. 295-
  

Last update Wed May 22 00:37:35 2013 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page