8. Asian Test Symposium 1999: Shanghai, China

ATPG Related Approaches I

• Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara:
  A Method of Test Generation for Weakly Testable Data Paths Using Test Knowledge Extracted from RTL Description. 5-12
  
• Junichi Hirase, Shinichi Yoshimura, Tomohisa Sczaki:
  Automatic Test Pattern Generation for Improving the Fault Coverage of Microprocessors. 13-19
  
• Seiji Kajihara, Atsushi Murakami, Tomohisa Kaneko:
  On Compact Test Sets for Multiple Stuck-at Faults for Large Circuits. 20-24
  
• Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada:
  Identification of Feedback Bridging Faults with Oscillation. 25-
  

Delay Fault & Memory Test

• A. J. van de Goor, J. E. Simonse:
  Defining SRAM Resistive Defects and Their Simulation Stimuli. 33-40
  
• Irith Pomeranz, Sudhakar M. Reddy:
  Vector-Based Functional Fault Models for Delay Faults. 41-46
  
• G. Sidiropoulos, Haridimos T. Vergos, Dimitris Nikolos:
  Easily Path Delay Fault Testable Non-Restoring Cellular Array Dividers. 47-52
  
• Said Hamdioui, A. J. van de Goor:
  March Tests for Word-Oriented Two-Port Memories. 53-
  

ATPG Related Approaches II

• Shiyi Xu, Tukwasibwe Justaf Frank:
  An Evaluation of Test Generation Algorithms for combinational Circuits. 63-69
  
• Zhide Zeng, Jihua Chen, Hefeng Cao:
  Research and Implementation of a High Speed Test Generation for Ultra Large Scale Combinational Circuits. 70-74
  
• Irith Pomeranz, Sudhakar M. Reddy:
  Pattern Sensitivity: A Property to Guide Test Generation for Combinational Circuits. 75-80
  
• Jing-Jou Tang:
  An Accurate Logic Threshold Voltages Determination Model for CMOS Gates to Facilitate Test Generation and Fault Simulation. 81-
  

BIST Related Approaches

• Patrick Girard, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch:
  Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption. 89-94
  
• Wenyi Feng, Wei-Kang Huang, Fred J. Meyer, Fabrizio Lombardi:
  A BIST TPG Approach for Interconnect Testing With the IEEE 1149.1 STD. 95-100
  
• Albrecht P. Stroele, Frank Mayer:
  Test Scheduling with Loop Folding and Its Application to Test Configurations with Accumulators. 101-106
  
• C. P. Ravikumar, Ashutosh Verma, Gaurav Chandra:
  A Polynomial-Time Algorithm for Power Constrained Testing of Core Based Systems. 107-112
  
• Serge N. Demidenko, Kenneth V. Lever:
  Accelerating Test Data Processin. 113-
  

Test Generation, Diagnosis, & Verification

• Arabi Keshk, Kozo Kinoshita, Yukiya Miura:
  Procedure to Overcome the Byzantine General's Problem for Bridging Faults in CMOS Circuits. 121-126
  
• Chanyutt Arjhan, Raghvendra G. Deshmukh:
  A Novel Fault-Detection Technique for The Parallel Multipliers and Dividers. 127-132
  
• Zhide Zeng, Jihua Chen, Pengxia Liu:
  A Fault Partitioning Method in Parallel Test Generation for Large Scale VLSI Circuits. 133-
  

IDDQ Test

• Yoshinobu Higami, Yuzo Takamatsu, Kewal K. Saluja, Kozo Kinoshita:
  Fault Simulation Techniques to Reduce IDDQ Measurement Vectors for Sequential Circuits. 141-146
  
• Hideyuki Ichihara, Kozo Kinoshita, Seiji Kajihara:
  On an Effective Selection of IDDQ Measurement Vectors for Sequential Circuits. 147-152
  
• Junichi Hirase, Naoki Shindou, Kouji Akahori:
  Scan Chain Diagnosis Using IDDQ Current Measurement. 153-157
  
• Arabi Keshk, Kozo Kinoshita, Yukiya Miura:
  IDDQ Current Dependency on Test Vectors and Bridging Resistance. 158-163
  
• Tsuyoshi Shinogi, Terumine Hayashi:
  A Parallel Generation System of Compact IDDQ Test Sets for Large Combinational Circuits. 164-
  

Sequential Circuit Test

• Hsing-Chung Liang, Chung-Len Lee:
  An Effective Methodology for Mixed Scan and Reset Design Based on Test Generation and Structure of Sequential Circuits. 173-178
  
• Li Shen:
  Genetic Algorithm Based Test Generation for Sequential Circuits. 179-184
  
• Mario H. Konijnenburg, Hans van der Linden, A. J. van de Goor:
  Fault (In)Dependent Cost Estimates and Conflict-Directed Backtracking to Guide Sequential Circuit Test Generation. 185-191
  
• Toshinori Hosokawa, Toshihiro Hiraoka, Tomoo Inoue, Hideo Fujiwara:
  Static and Dynamic Test Sequence Compaction Methods for Acyclic Sequential Circuits Using a Time Expansion Model. 192-
  

Fault-Tolerant & Diagnosis

• Yasuyuki Taniguchi, Naotake Kamiura, Yutaka Hata, Nobuyuki Matsui:
  Activation Function Manipulation for Fault Tolerant Feedforward Neural Networks. 203-208
  
• Tao Zhang, Dongcheng Hu, Shiyuan Yang:
  Fault-Tolerant Analysis of Feedback Neural Networks with Threshold Neurons. 209-213
  
• Jianhua Gao, Shihuang Shao:
  Fault-Tolerant Strategies and Their Design Methods for Application Software. 214-217
  
• Chenglian Peng, Baifeng Wu, Xiaoguang Sun:
  Test by Distributed Monitoring. 218-
  

Analog Circuits Test

• Abdelhakim Khouas, Mohamed Dessouky, Anne Derieux:
  Optimized Statistical Analog Fault Simulation. 227-232
  
• Chauchin Su, Yue-Tsang Chen, Chung-Len Lee:
  Analog Metrology and Stimulus Selection in a Noisy Environment. 233-238
  
• Sam D. Huynh, Jinyan Zhang, Seongwon Kim, Giri Devarayanadurg, Mani Soma:
  Efficient Test Set Design for Analog and Mixed-Signal Circuits and Systems. 239-
  

Railway Signaling Software

• Fangmei Wu, Meng Li:
  Railway Signaling Safety-critical Software Testing Based on Dynamic Decision Table. 247-250
  
• Zhongwei Xu, Fangmei Wu:
  A Novel Testing Approach for Safety-Critical Software. 251-255
  
• Haiying Tu, Fangmei Wu:
  How to Design an Environment Simulator for Safety Critical Software Testing. 256-
  

DFT

• Debesh Kumar Das, Satoshi Ohtake, Hideo Fujiwara:
  New DFT Techniques of Non-Scan Sequential Circuits with Complete Fault Efficiency. 263-268
  
• Teruhiko Yamada, Toshinori Kotake, Hiroshi Takahashi, Koji Yamazaki:
  Identification of Redundant Crosspoint Faults in Sequential PLAs with Fault-Free Hardware Reset. 269-274
  
• Abhijit Jas, Kartik Mohanram, Nur A. Touba:
  An Embedded Core DFT Scheme to Obtain Highly Compressed Test Sets. 275-
  

Software Test & Verification

• Youngchul Kim, C. Robert Carlson:
  Scenario Based Integration Testing for Object-Oriented Software Development. 283-288
  
• Huaikou Miao, Xiaolei Gao, Ling Liu:
  An Approach to Testing the Nonexistence of Initial State in Z Specifications. 289-294
  
• Ian Ho, Jin-Cherng Lin:
  Generating Test Cases for Real-Time Software by Time Petri Nets Model. 295-300
  
• Shyue-Kung Lu, Tsung-Ying Lee, Cheng-Wen Wu:
  Defect Level Prediction Using Multi-Model Fault Coverage. 301-
  

Scan & Boundary Scan

• Tomoya Takasaki, Hideo Fujiwara, Tomoo Inoue:
  A High-Level Synthesis Approach to Partial Scan Design Based on Acyclic Structure. 309-314
  
• Tsung-Chu Huang, Kuen-Jong Lee:
  An Input Control Technique for Power Reduction in Scan Circuits During Test Application. 315-320
  
• Xinghao Chen, Thomas J. Snethen, Joe Swenton, Ron Walther:
  A Simplified Method for Testing the IBM Pipeline Partial-Scan Microprocessor. 321-326
  
• Zulan Huang, Yizheng Ye, Zhigang Mao:
  A New Algorithm for Retiming-Based Partial Scan. 327-
  

Beam Testing in Japan

• Katsuyoshi Miura, Koji Nakamae, Hiromu Fujioka:
  Intelligent EB Test System for Automatic VLSI Fault Tracing. 335-341
  
• Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu, Nobuhiro Yanagida:
  Multiple Fault Diagnosis in Logic Circuits Using EB Tester and Multiple/Single Fault Simulators. 341-346
  
• Reisuke Shimoda, Takaki Yoshida, Masafumi Watari, Yasuhiro Toyota, Kiyokazu Nishi, Akira Motohara:
  Practical Application of Automated Fault Diagnosis for Stuck-at, Bridging, and Measurement Condition Dependent Faults in Fully Scanned Sequential Circuits. 347-
  

FPGA Test

• Yinlei Yu, Jian Xu, Wei-Kang Huang, Fabrizio Lombardi:
  Minimizing the Number of Programming Steps for Diagnosis of Interconnect Faults in FPGAs. 357-362
  
• Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian:
  Minimizing the Number of Test Configurations for Different FPGA Families. 363-368
  
• Abderrahim Doumar, Hideo Ito:
  Testing the Logic Cells and Interconnect Resources for FPGAs. 369-374
  
• Lan Zhao, D. M. H. Walker, Fabrizio Lombardi:
  IDDQ Testing of Input/Output Resources of SRAM-Based FPGAs. 375-
  

Beam Testing in Japan

• Kiyoshi Nikawa, Shoji Inoue, Kazuyuki Morimoto, Shinya Sone:
  Failure Analysis Case Studies Using the IR-OBIRCH (Infrared Optical Beam Induced Resistance CHange) Method. 383-388
  
• Takahide Sakata, Hideyuki Takahashi, Tetsu Sekine, Toshiya Ogiwara:
  Investigation of Ga Contamination Due to Analysis by Dual Beam FIB. 389-393
  
• Kiyoshi Nikawa, Shoji Inoue, Kazuyuki Morimoto, Shinya Sone:
  Failure Analysis Case Studies Using the IR-OBIRCH (Infrared Optical Beam Induced Resistance CHange) Method. 394-
  

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