• 
  11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA. IEEE Computer Society 2002 ISBN 0-7695-1825-7

Test Generation

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  Yun Shao, Irith Pomeranz, Sudhakar M. Reddy: On Generating High Quality Tests for Transition Faults. 1
• 
  Ilia Polian, Irith Pomeranz, Bernd Becker: Exact Computation of Maximally Dominating Faults and Its Application to n-Detection Tests. 2-14
• 
  Shiyi Xu, Jianwen Chen: Maximum Distance Testing. 15-

On-Line Testing

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  Junichi Hirase: High Precision Result Evaluation of VLSI. 21-26
• 
  Jing-ling Yang, Oliver Chiu-sing Choy, Cheong-fat Chan, Kong-Pong Pun: A Totally Self-Checking Dynamic Asynchronous Datapath. 27-32
• 
  Petros Drineas, Yiorgos Makris: Non-Intrusive Design of Concurrently Self-Testable FSMs. 33-

Analog and Mixed Signal Testing

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  Jacob Savir, Zhen Guo: Test Limitations of Parametric Faults in Analog Circuits. 39-44
• 
  Masahiro Ishida, Takahiro J. Yamaguchi, Mani Soma, Hirobumi Musha: Effects of Amplitude Modulation in Jitter Tolerance Measurements of Communication Devices. 45-48
• 
  Hao-Chiao Hong, Jiun-Lang Huang, Kwang-Ting Cheng, Cheng-Wen Wu: On-chip Analog Response Extraction with 1-Bit ? - Modulators. 49-

Test Set Compaction

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  Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka: A State Reduction Method for Non-Scan Based FSM Testing with Don't Care Inputs Identification Technique. 55-60
• 
  Irith Pomeranz, Sudhakar M. Reddy: Improving the Efficiency of Static Compaction Based on Chronological Order Enumeration of Test Sequences. 61-66
• 
  Seiji Kajihara, Kenjiro Taniguchi, Kohei Miyase, Irith Pomeranz, Sudhakar M. Reddy: Test Data Compression Using Don?t-Care Identification and Statistical Encoding. 67-

Design for Testability

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  Atlaf Ul Amin, Satoshi Ohtake, Hideo Fujiwara: Design for Two-Pattern Testability of Controller-Data Path Circuits. 73-79
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  Takaki Yoshida, Masafumi Watari: MD-SCAN Method for Low Power Scan Testing. 80-85
• 
  Dong Xiang, Shan Gu, Hideo Fujiwara: Non-Scan Design for Testability Based on Fault Oriented Conflict Analysis. 86-

Memory Testing 1

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  Alfredo Benso, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto: Specification and Design of a New Memory Fault Simulator. 92-97
• 
  Zaid Al-Ars, A. J. van de Goor: DRAM Specific Approximation of the Faulty Behavior of Cell Defects. 98-103
• 
  Shu-Rong Lee, Ming-Jun Hsiao, Tsin-Yuan Chang: An Access Timing Measurement Unit of Embedded Memory. 104-

Delay Fault Testing

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  Irith Pomeranz, Sudhakar M. Reddy: A Partitioning and Storage Based Built-In Test Pattern Generation Method for Delay Faults in Scan Circuits. 110-115
• 
  Lihong Tong, Kazuki Suzuki, Hideo Ito: Optimal Seed Generation for Delay Fault Detection BIST. 116-121
• 
  Octavian Petre, Hans G. Kerkhoff: On-Chip Tap-Delay Measurements for a Digital Delay-Line Used in High-Speed Inter-Chip Data Communications. 122-

Test Synthesis

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  Tomoo Inoue, Tomokazu Miura, Akio Tamura, Hideo Fujiwara: A Scheduling Method in High-Level Synthesis for Acyclic Partial Scan Design. 128-133
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  Yiorgos Makris, Alex Orailoglu: Test Requirement Analysis for Low Cost Hierarchical Test Path Construction. 134-139
• 
  P. Zhongliang: Testable Realizations for ESOP Expressions of Logic Functions. 140-

Memory Testing 2

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  Hong-Sik Kim, Sungho Kang: DPSC SRAM Transparent Test Algorithm. 145-150
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  Xuemei Zhao, Yizheng Yu, Chunxu Chen: Tests for Word-Oriented Content Addressable Memories. 151-156
• 
  Swarup Bhunia, Hai Li, Kaushik Roy: A High Performance IDDQ Testable Cache for Scaled CMOS Technologies. 157-

Crosstalk Fault Testing

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  Wichian Sirisaengtaksin, Sandeep K. Gupta: Enhanced Crosstalk Fault Model and Methodology to Generate Tests for Arbitrary Inter-core Interconnect Topology. 163-169
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  Ming Shae Wu, Chung-Len Lee, Chi Peng Chang, Jwu E. Chen: A Testing Scheme for Crosstalk Faults Based on the Oscillation Test Signal. 170-175
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  Kazuya Shimizu, Noriyoshi Itazaki, Kozo Kinoshita: Crosstalk Fault Reduction and Simulation for Clock-Delayed Domino Circuits. 176-181
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  Marong Phadoongsidhi, Kim T. Le, Kewal K. Saluja: A Concurrent Fault Simulation for Crosstalk Faults in Sequential Circuits. 182-

Built-in Self Test 1

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  Santanu Chattopadhyay: Efficient Circuit Specific Pseudoexhaustive Testing with Cellular Automata. 188-193
• 
  Emil Gizdarski, Hideo Fujiwara: Fault Set Partition for Efficient Width Compression. 194-199
• 
  Nan-Cheng Li, Sying-Jyan Wang: A Reseeding Technique for LFSR-Based BIST Applications. 200-205
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  Emmanouil Kalligeros, Xrysovalantis Kavousianos, Dimitris Nikolos: A ROMless LFSR Reseeding Scheme for Scan-based BIST. 206-

Fault-Tolerance

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  Min-Kyu Joo, Jin-Hyung Kim, Yoon-Hwa Choi: A Fault-Tolerant Architecture for Symmetric Block Ciphers. 212-217
• 
  Fabian Vargas, Djones Lettnin, Diogo B. Brum, Dárcio Prestes: A New Learning Approach to Design Fault Tolerant ANNs: Finally a Zero HW-SW Overhead. 218-223
• 
  Fabian Vargas, Rubem Dutra Ribeiro Fagundes, Daniel Barros Jr.: Experimental Results of a Recovery Block Scheme to Handle Noise in Speech Recognition Systems. 224-229
• 
  Shyue-Kung Lu, Chien-Hung Yeh: Easily Testable and Fault-Tolerant Design of FFT Butterfly Networks. 230-

Fault Detection and Diagnosis

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  Shyue-Kung Lu, Chung-Yang Chen: Fault Detection and Fault Diagnosis Technoques for Lookup Table FPGA's. 236-241
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  Keith J. Keller, Hiroshi Takahashi, Kim T. Le, Kewal K. Saluja, Yuzo Takamatsu: Reduction of Target Fault List for Crosstalk-Induced Delay Faults by using Layout Constraints. 242-247
• 
  Shi-Yu Huang: Diagnosis Of Byzantine Open-Segment Faults. 248-

Built-in Self Test 2

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  Alexej Dmitriev, Michael Gössel, Krishnendu Chakrabarty: Robust Space Compaction of Test Responses. 254-259
• 
  Niloy Ganguly, Anindyasundar Nandi, Sukanta Das, Biplab K. Sikdar, Parimal Pal Chaudhuri: An Evolutionary Strategy To Design An On-Chip Test Pattern Generator Without Prohibited Pattern Set (PPS). 260-265
• 
  Sheng-Hung Hsieh, Ming-Jun Hsiao, Tsin-Yuan Chang: An Embedded Built-In-Self-Test Approach for Analog-to-Digital Converters. 266-

Software Testing

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  Sousuke Amasaki, Takashi Yoshitomi, Osamu Mizuno, Tohru Kikuno, Yasunari Takagi: Statistical Analysis of Time Series Data on the Number of Faults Detected by Statistical Analysis of Time Series Data on the Number of Faults Detected by Software Testing. 272-277
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  Jin-Cherng Lin, Szu-Wen Lin: An Analytic Software Testability Model. 278-283
• 
  Juichi Takahashi, Yoshiaki Kakuda: Effective Automated Testing: A Solution of Graphical Object Verification. 284-

Special Session - Test Strategies and Case Studies for SoC in Industries

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  Kazumi Hatayama, Michinobu Nakao, Yasuo Sato: At-Speed Built-in Test for Logic Circuits with Multiple Clocks. 292-297
• 
  Masayoshi Yoshimura, Toshinori Hosokawa, Mitsuyasu Ohta: A Test Point Insertion Method to Reduce the Number of Test Patterns. 298-304
• 
  Hiroshi Date, Toshinori Hosokawa, Michiaki Muraoka: A SoC Test Strategy Based on a Non-Scan DFT Method. 305-310
• 
  Kazuhiko Iijima, Armagan Akar, Charlie McDonald, Dwayne Burek: Embedded Test Solution as a Breakthrough in Reducing Cost of Test for System on Chips. 311-316
• 
  Rohit Kapur, Thomas W. Williams: Manufacturing Test of SoCs. 317-319
• 
  Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen: Recent Advances in Test Planning for Modular Testing of Core-Based SOCs. 320-

Test Power Reduction

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  Yoshinobu Higami, Shin-ya Kobayashi, Yuzo Takamatsu: A Method to Reduce Power Dissipation during Test for Sequential Circuits. 326-331
• 
  Zuying Luo, Xiaowei Li, Huawei Li, Shiyuan Yang, Yinghua Min: Test Power Optimization Techniques for CMOS Circuits. 332-337
• 
  Kuen-Jong Lee, Jih-Jeen Chen: Reducing Test Application Time and Power Dissipation for Scan-Based Testing via Multiple Clock Disabling. 338-

System-on-Chip Testing 1

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  Jaehoon Song, Sungju Park: A Simple Wrapped Core Linking Module for SoC Test Access. 344-349
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  K. Y. Ko, Mike W. T. Wong, Y. S. Lee: Testing System-On-Chip by Summations of Cores? Test Output Voltages. 350-355
• 
  Chih-Wea Wang, Jing-Reng Huang, Yen-Fu Lin, Kuo-Liang Cheng, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin: Test Scheduling of BISTed Memory Cores for SOC. 356-

Verification and Simulation

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  Tai-Ying Jiang, Chien-Nan Jimmy Liu, Jing-Yang Jou: Effective Error Diagnosis for RTL Designs in HDLs. 362-367
• 
  Fulvio Corno, Gianluca Cumani, Matteo Sonza Reorda, Giovanni Squillero: Evolutionary Test Program Induction for Microprocessor Design Verification. 368-373
• 
  Shahrzad Mirkhani, Meisam Lavasani, Zainalabedin Navabi: Hierarchical Fault Simulation Using Behavioral and Gate Level Hardware Models. 374-

Test Systems

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  Harald J. Zainzinger: Testing Embedded Systems by Using a C++ Script Interpreter. 380-385
• 
  Rochit Rajsuman: Extending EDA Environment From Design to Test. 386-391
• 
  Kazuhiro Yamada, Yoshikazu Takahashi: Vector Memory Expansion System For T33xx Logic Tester. 392-

System-on-Chip Testing 2

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  Erik Larsson, Klas Arvidsson, Hideo Fujiwara, Zebo Peng: Integrated Test Scheduling, Test Parallelization and TAMDesign. 397-404
• 
  Yu Huang, Sudhakar M. Reddy, Wu-Tung Cheng: Core - Clustering Based SOC Test Scheduling Optimization. 405-410
• 
  Huan-Shan Hsu, Jing-Reng Huang, Kuo-Liang Cheng, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin: Test Scheduling and Test Access Architecture Optimization for System-on-Chip. 411-

Current Testing

• 
  Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Toshifumi Kobayashi, Tsutomu Hondo: CMOS Floating Gate Defect Detection Using I DDQ Test with DC Power Supply. 417-422
• 
  Hiroyuki Yotsuyanagi, Masaki Hashizume, Takeomi Tamesada: Test Time Reduction for I DDQ Testing by Arranging Test Vectors. 423-428
• 
  Shambhu J. Upadhyaya, Jae Min Lee, Padmanabhan Nair: Time Slot Specification Based Approach to Analog Fault Diagnosis Using Built-in Current Sensors and Test Point Insertion. 429-434