13. Asian Test Symposium 2004: Kenting, Taiwan

Session A1: SOC Testing

• Qiang Xu, Nicola Nicolici:
  Multi-Frequency Test Access Mechanism Design for Modular SOC Testing. 2-7
  
• Yinhe Han, Yu Hu, Huawei Li, Xiaowei Li, Anshuman Chandra:
  Rapid and Energy-Efficient Testing for Embedded Cores. 8-13
  
• Jianhui Xing, Hong Wang, Shiyuan Yang:
  Constructing Transparency Paths for IP Cores Using Greedy Searching Strategy. 14-19
  
• Aristides Efthymiou, John Bainbridge, Douglas A. Edwards:
  Adding Testability to an Asynchronous Interconnect for GALS SoC. 20-23
  

Session B1: Low-Power Testing

• Kuen-Jong Lee, Shaing-Jer Hsu, Chia-Ming Ho:
  Test Power Reduction with Multiple Capture Orders. 26-31
  
• Zhiqiang You, Ken-ichi Yamaguchi, Michiko Inoue, Jacob Savir, Hideo Fujiwara:
  Power-Constrained DFT Algorithms for Non-Scan BIST-able RTL Data Paths. 32-39
  
• Nan-Cheng Lai, Sying-Jyan Wang, Yu-Hsuan Fu:
  Low Power BIST with Smoother and Scan-Chain Reorder . 40-45
  
• Yoshinobu Higami, Seiji Kajihara, Shin-ya Kobayashi, Yuzo Takamatsu:
  Techniques for Finding Xs in Test Sequences for Sequential Circuits and Applications to Test Length/Power Reduction. 46-49
  

Session C1: Analog BIST

• Hsin-Wen Ting, Bin-Da Liu, Soon-Jyh Chang:
  A Time Domain Built-In Self-Test Methodology for SNDR and ENOB Tests of Analog-to-Digital Converters. 52-57
  
• Guan-Xun Chen, Chung-Len Lee, Jwu E. Chen:
  A New BIST Scheme Based on a Summing-into-Timing-Signal Principle with Self Calibration for the DAC. 58-61
  
• Hao-Chiao Hong, Cheng-Wen Wu, Kwang-Ting Cheng:
  A Signa-Delta Modulation Based Analog BIST System with a Wide Bandwidth Fifth-Order Analog Response Extractor for Diagnosis Purpose. 62-67
  
• Soumendu Bhattacharya, Abhijit Chatterjee:
  A Built-In Loopback Test Methodology for RF Transceiver Circuits Using Embedded Sensor Circuits. 68-73
  

Session A2: Advanced DFT

• Kohei Miyase, Seiji Kajihara, Sudhakar M. Reddy:
  Multiple Scan Tree Design with Test Vector Modification. 76-81
  
• Jiann-Chyi Rau, Ching-Hsiu Lin, Jun-Yi Chang:
  An Efficient Low-Overhead Policy for Constructing Multiple Scan-Chains. 82-87
  
• Dong Xiang, Ming-Jing Chen, Kaiwei Li, Yu-Liang Wu:
  Scan-Based BIST Using an Improved Scan Forest Architecture. 88-93
  
• Il-soo Lee, Yong Min Hur, Tony Ambler:
  The Efficient Multiple Scan Chain Architecture Reducing Power Dissipation and Test Time. 94-97
  

Session B2: Fault Analysis

• John P. Hayes, Ilia Polian, Bernd Becker:
  Testing for Missing-Gate Faults in Reversible Circuits. 100-105
  
• Irith Pomeranz, Sudhakar M. Reddy:
  Properties of Maximally Dominating Faults. 106-111
  
• Masaki Hashizume, Daisuke Yoneda, Hiroyuki Yotsuyanagi, Tetsuo Tada, Takeshi Koyama, Ikuro Morita, Takeomi Tamesada:
  I_DDQ Test Method Based on Wavelet Transformation for Noisy Current Measurement Environment. 112-117
  
• Klaus Rothbart, Ulrich Neffe, Christian Steger, Reinhold Weiss, Edgar Rieger, Andreas Mühlberger:
  High Level Fault Injection for Attack Simulation in Smart Cards. 118-121
  

Session C2: Cross-Talk Testing

• Melvin A. Breuer, Sandeep K. Gupta, Shahin Nazarian:
  Efficient Identification of Crosstalk Induced Slowdown Targets. 124-131
  
• Wichian Sirisaengtaksin, Sandeep K. Gupta:
  Modeling and Testing Crosstalk Faults in Inter-Core Interconnects that Include Tri-State and Bi-Directional Nets. 132-139
  
• Chung Liang Chen, Chung-Len Lee, Ming Shae Wu:
  A New Path Delay Test Scheme Based on Path Delay Inertia. 140-144
  
• Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen:
  A Unified Approach to Detecting Crosstalk Faults of Interconnects in Deep Sub-Micron VLSI. 145-150
  

Session A3: Functional Testing

• Kazuko Kambe, Michiko Inoue, Hideo Fujiwara:
  Efficient Template Generation for Instruction-Based Self-Test of Processor Cores. 152-157
  
• Saeed Shamshiri, Hadi Esmaeilzadeh, Zainalabedin Navabi:
  Test Instruction Set (TIS) for High Level Self-Testing of CPU Cores. 158-163
  
• Chin-Lung Chuang, Dong-Jung Lu, Chien-Nan Jimmy Liu:
  A Snapshot Method to Provide Full Visibility for Functional Debugging Using FPGA. 164-169
  
• Shiyi Xu:
  A Systematic Way of Functional Testing for VLSI Chips. 170-175
  

Session B3: Logic BIST

• Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz:
  Weighted Pseudo-Random BIST for N-Detection of Single Stuck-at Faults. 178-183
  
• Santosh Biswas, Siddhartha Mukhopadhyay, Amit Patra:
  A BIST Approach to On-Line Monitoring of Digital VLSI Circuits: A CAD Tool. 184-189
  
• Masayuki Arai, Harunobu Kurokawa, Kenichi Ichino, Satoshi Fukumoto, Kazuhiko Iwasaki:
  Seed Selection Procedure for LFSR-Based BIST with Multiple Scan Chains and Phase Shifters. 190-195
  
• Sukanta Das, Anirban Kundu, Biplab K. Sikdar:
  Nonlinear CA Based Design of Test Set Generator Targeting Pseudo-Random Pattern Resistant Faults. 196-201
  

Session C3: Fault Diagnosis

• Wu-Tung Cheng, Kun-Han Tsai, Yu Huang, Nagesh Tamarapalli, Janusz Rajski:
  Compactor Independent Direct Diagnosis. 204-209
  
• Swaroop Ghosh, K. W. Lai, Wen-Ben Jone, Shih-Chieh Chang:
  Scan Chain Fault Identification Using Weight-Based Codes for SoC Circuits. 210-215
  
• Hiroshi Takahashi, Yukihiro Yamamoto, Yoshinobu Higami, Yuzo Takamatsu:
  Enhancing BIST Based Single/Multiple Stuck-at Fault Diagnosis by Ambiguous Test Set. 216-221
  
• Yuichi Sato, Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamatsu:
  Failure Analysis of Open Faults by Using Detecting/Un-detecting Information on Tests. 222-227
  

Session A4: SOC Test Scheduling

• Zhiyuan He, Gert Jervan, Zebo Peng, Petru Eles:
  Hybrid BIST Test Scheduling Based on Defect Probabilities. 230-235
  
• Yu Hu, Yinhe Han, Huawei Li, Tao Lv, Xiaowei Li:
  Pair Balance-Based Test Scheduling for SOCs. 236-241
  
• Jung-Been Im, Sunghoon Chun, Geunbae Kim, Jin-Ho Ahn, Sungho Kang:
  RAIN (RAndom Insertion) Scheduling Algorithm for SoC Test. 242-247
  
• Wei-Lun Wang:
  March Based Memory Core Test Scheduling for SOC. 248-253
  
• Stina Edbom, Erik Larsson:
  An Integrated Technique for Test Vector Selection and Test Scheduling under Test Time Constraint. 254-257
  

Session B4: Memory Testing

• Chih-Tsun Huang, Jen-Chieh Yeh, Yuan-Yuan Shih, Rei-Fu Huang, Cheng-Wen Wu:
  On Test and Diagnostics of Flash Memories. 260-265
  
• Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Simone Borri, Magali Bastian Hage-Hassan:
  Resistive-Open Defects in Embedded-SRAM Core Cells: Analysis and March Test Solution. 266-271
  
• Yi-Ming Sheng, Ming-Jun Hsiao, Tsin-Yuan Chang:
  A Measurement Unit for Input Signal Analysis of SRAM Sense Amplifier. 272-276
  
• Jin-Fu Li, Chao-Da Huang:
  An Efficient Diagnosis Scheme for Random Access Memories. 277-282
  
• Said Hamdioui, John Delos Reyes, Zaid Al-Ars:
  Evaluation of Intra-Word Faults in Word-Oriented RAMs. 283-288
  

Session C4: Analog Testing

• Jochen Rivoir:
  Low-Cost Analog Signal Generation Using a Pulse-Density Modulated Digital ATE Channel. 290-295
  
• Chih-Haur Huang, Kuen-Jong Lee, Soon-Jyh Chang:
  A Low-Cost Diagnosis Methodology for Pipelined A/D Converters. 296-301
  
• Ganesh Srinivasan, Shalabh Goyal, Abhijit Chatterjee:
  Reconfiguration for Enhanced ALternate Test (REALTest) of Analog Circuits. 302-307
  
• C. C. Su, C. S. Chang, H. W. Huang, D. S. Tu, C. L. Lee, Jerry C. H. Lin:
  Dynamic Analog Testing via ATE Digital Test Channels. 308-312
  

Session A5: Testable Design

• Mike W. T. Wong, Yubin Zhang:
  Design and Implementation of Self-Testable Full Range Window Comparator. 314-318
  
• Jin-Fu Li, Chih-Chiang Hsu:
  Efficient Test Methodologies for Conditional Sum Adders. 319-324
  
• Dilip P. Vasudevan, Parag K. Lala, James Patrick Parkerson:
  A Novel Approach for On-line Testable Reversible Logic Circuit Desig. 325-330
  
• Sukanta Das, Biplab K. Sikdar, Parimal Pal Chaudhuri:
  Nonlinear CA Based Scalable Design of On-Chip TPG for Multiple Cores. 331-334
  

Session B5: Testability Analysis

• Guanghui Li, Xiaowei Li:
  Circuit-Width Based Heuristic for Boolean Reasoning. 336-341
  
• Debesh Kumar Das, Tomoo Inoue, Susanta Chakraborty, Hideo Fujiwara:
  Max-Testable Class of Sequential Circuits having Combinational Test Generation Complexity. 342-347
  
• Chia Yee Ooi, Hideo Fujiwara:
  Classification of Sequential Circuits Based on ?k Notation. 348-353
  
• Shiy Xu, E. Edirisuriya:
  A New Way of Detecting Reconvergent Fanout Branch Pairs in Logic Circuits. 354-357
  

Session C5: Yield and Reliability

• Chin-Long Wey, Meng-Yao Liu:
  Burn-In Stress Test of Analog CMOS ICs. 360-365
  
• Rei-Fu Huang, Chin-Lung Su, Cheng-Wen Wu, Shen-Tien Lin, Kun-Lun Luo, Yeong-Jar Chang:
  Fail Pattern Identification for Memory Built-In Self-Repair. 366-371
  
• Haihua Yan, Adit D. Singh:
  Reduce Yield Loss in Delay Defect Detection in Slack Interval. 372-377
  
• Chin-Yu Huang, Chu-Ti Lin, Chuan-Ching Sue:
  Considering Fault Dependency and Debugging Time Lag in Reliability Growth Modeling during Software Testing. 378-383
  

Session A6: Fault Tolerance

• Melvin A. Breuer:
  Intelligible Test Techniques to Support Error-Tolerance. 386-393
  
• Jin-Min Yang, Da-Fang Zhang:
  Bounding Rollback-Recovery of Large Distributed Computation in WAN Environment. 394-399
  
• Chuan-Ching Sue, Jun-Ying Yeh, Chin-Yu Huang:
  Full Restoration of Multiple Faults in WDM Networks without Wavelength Conversion. 400-405
  
• Naotake Kamiura, Teijiro Isokawa, Nobuyuki Matsui:
  On Improvement in Fault Tolerance of Hopfield Neural Networks. 406-411
  

Session B6: FPGA Testing and Test Reduction

• Shyue-Kung Lu, Hung-Chin Wu, Shoei-Jia Yan, Yu-Cheng Tsai:
  Testing and Diagnosis Techniques for LUT-Based FPGA's. 414-419
  
• Donghoon Han, Abhijit Chatterjee:
  Device Resizing Based Optimization of Analog Circuits for Reduced Test Cost: Cost Metric and Case Study. 420-425
  
• Hideyuki Ichihara, Masakuni Ochi, Michihiro Shintani, Tomoo Inoue:
  A Test Decompression Scheme for Variable-Length Coding. 426-431
  
• Youhua Shi, Shinji Kimura, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki:
  Alternative Run-Length Coding through Scan Chain Reconfiguration for Joint Minimization of Test Data Volume and Power Consumption in Scan Test. 432-437
  

Session C6: Delay Testing

• Lei Wang, Sandeep K. Gupta, Melvin A. Breuer:
  Modeling and Simulation for Crosstalk Aggravated by Weak-Bridge Defects between On-Chip Interconnects. 440-447
  
• Irith Pomeranz, Sudhakar M. Reddy:
  A Postprocessing Procedure of Test Enrichment for Path Delay Faults. 448-453
  
• Ho Fai Ko, Nicola Nicolici:
  Functional Scan Chain Design at RTL for Skewed-Load Delay Fault Testing. 454-459
  
• Antonio Zenteno, Víctor H. Champac, Michel Renovell, Florence Azaïs:
  Analysis and Attenuation Proposal in Ground Bounce. 460-463
  

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