CASES 2009: Grenoble, France

Special session I

• Krishna V. Palem, Lakshmi N. Chakrapani, Zvi M. Kedem, Lingamneni Avinash, Kirthi Krishna Muntimadugu:
  Sustaining moore's law in embedded computing through probabilistic and approximate design: retrospects and prospects. 1-10
  
• M. Haykel Ben Jamaa, Gianfranco Cerofolini, Yusuf Leblebici, Giovanni De Micheli:
  Complete nanowire crossbar framework optimized for the multi-spacer patterning technique. 11-16
  
• Soon Fatt Yoon:
  III-V/Si integration: potential and outlook for integrated low power micro and nanosystems. 17-18
  

Compiler techniques for performance

• Rooju Chokshi, Krzysztof S. Berezowski, Aviral Shrivastava, Stanislaw J. Piestrak:
  Exploiting residue number system for power-efficient digital signal processing in embedded processors. 19-28
  
• Tao Li, Zhigang Sun, Wu Jigang, Xicheng Lu:
  Fast enumeration of maximal valid subgraphs for custom-instruction identification. 29-36
  
• Manoj Gupta, Fermín Sánchez, Josep Llosa:
  Hybrid multithreading for VLIW processors. 37-46
  
• Mouad Bahi, Christine Eisenbeis:
  Spatial complexity of reversibly computable DAG. 47-56
  

Parallelism, streams, and spilling

• Paul M. Carpenter, Alex Ramírez, Eduard Ayguadé:
  Mapping stream programs onto heterogeneous multiprocessor systems. 57-66
  
• Duo Liu, Zili Shao, Meng Wang, Minyi Guo, Jingling Xue:
  Optimal loop parallelization for maximizing iteration-level parallelism. 67-76
  
• Dietmar Ebner, Bernhard Scholz, Andreas Krall:
  Progressive spill code placement. 77-86
  
• Mahmut T. Kandemir, Yuanrui Zhang, Sai Prashanth Muralidhara, Ozcan Ozturk, Sri Hari Krishna Narayanan:
  Slicing based code parallelization for minimizing inter-processor communication. 87-96
  

Architectural optimizations

• Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose:
  Fine-grain performance scaling of soft vector processors. 97-106
  
• Yong Dou, Fei Xia, Jingfei Jiang:
  Fine-grained parallel application specific computing for RNA secondary structure prediction using SCFGS on FPGA. 107-116
  
• Garo Bournoutian, Alex Orailoglu:
  Reducing impact of cache miss stalls in embedded systems by extracting guaranteed independent instructions. 117-126
  
• Alexander Fell, Mythri Alle, Keshavan Varadarajan, Prasenjit Biswas, Saptarsi Das, Jugantor Chetia, S. K. Nandy, Ranjani Narayan:
  Streaming FFT on REDEFINE-v2: an application-architecture design space exploration. 127-136
  

Pervasive parallelism

• Jinho Seol, Hyotaek Shim, Jaegeuk Kim, Seungryoul Maeng:
  A buffer replacement algorithm exploiting multi-chip parallelism in solid state disks. 137-146
  
• Ian Gray, Neil C. Audsley:
  Exposing non-standard architectures to embedded software using compile-time virtualisation. 147-156
  
• Dan Fay, Li Shang, Dirk Grunwald:
  A platform for developing adaptable multicore applications. 157-166
  
• Fabian Scheler, Wanja Hofer, Benjamin Oechslein, Rudi Pfister, Wolfgang Schröder-Preikschat, Daniel Lohmann:
  Parallel, hardware-supported interrupt handling in an event-triggered real-time operating system. 167-174
  

Microfluidics, worst-case execution time, and cache optimization

• Jin Ouyang, Raghuveer Raghavendra, Sibin Mohan, Tao Zhang, Yuan Xie, Frank Mueller:
  CheckerCore: enhancing an FPGA soft core to capture worst-case execution times. 175-184
  
• Kapil Anand, Rajeev Barua:
  Instruction cache locking inside a binary rewriter. 185-194
  
• Elena Maftei, Paul Pop, Jan Madsen:
  Tabu search-based synthesis of dynamically reconfigurable digital microfluidic biochips. 195-204
  
• Partha S. Roop, Sidharta Andalam, Reinhard von Hanxleden, Simon Yuan, Claus Traulsen:
  Tight WCRT analysis of synchronous C programs. 205-214
  

Special session II

• Mark Hempstead, Gu-Yeon Wei, David Brooks:
  An accelerator-based wireless sensor network processor in 130nm CMOS. 215-222
  
• Priya Narasimhan, Rajeev Gandhi, Dan Rossi:
  Smartphone-based assistive technologies for the blind. 223-232
  
• Yuexuan Wang, Yongcai Wang, Xiao Qi, Liwen Xu:
  OPAIMS: open architecture precision agriculture information monitoring system. 233-240
  

Reliability and reconfigurability

• Yu Wang, Jiang Xu, Shengxi Huang, Weichen Liu, Huazhong Yang:
  A case study of on-chip sensor network in multiprocessor system-on-chip. 241-250
  
• Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, Fadi J. Kurdahi:
  A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache). 251-260
  
• Joseph Sloan, Rakesh Kumar:
  Towards scalable reliability frameworks for error prone CMPs. 261-270
  
• Yongjun Park, Hyunchul Park, Scott A. Mahlke:
  CGRA express: accelerating execution using dynamic operation fusion. 271-280
  
• Mark S. K. Lau, Keck Voon Ling, Yun-Chung Chu:
  Energy-aware probabilistic multiplier: design and analysis. 281-290
  

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