13. CAV 2001:
Paris, France
Gérard Berry, Hubert Comon, Alain Finkel (Eds.):
Computer Aided Verification, 13th International Conference, CAV 2001, Paris, France, July 18-22, 2001, Proceedings.
Lecture Notes in Computer Science 2102 Springer 2001, ISBN 3-540-42345-1
Invited Talk
Model Checking and Theorem Proving
Automata Techniques
Verification Core Technology
BDD and Decision Procedures
Abstraction and Refinement
Combinations
Tool Presentations:
Rewriting and Theorem-Proving Techniques
- Miroslav N. Velev, Randal E. Bryant:
EVC: A Validity Checker for the Logic of Equality with Uninterpreted Functions and Memories, Exploiting Positive Equality, and Conservative Transformations.
235-240

- Dawn Xiaodong Song, Adrian Perrig, Doantam Phan:
AGVI - Automatic Generation, Verification, and Implementation of Security Protocols.
241-245

- Jean-Christophe Filliâtre, Sam Owre, Harald Rueß, Natarajan Shankar:
ICS: Integrated Canonizer and Solver.
246-249

- Stefan Blom, Wan Fokkink, Jan Friso Groote, Izak van Langevelde, Bert Lisser, Jaco van de Pol:
µCRL: A Toolset for Analysing Algebraic Specifications.
250-254

- Martin Leucker, Thomas Noll:
Truth/SLC - A Parallel Verification Platform for Concurrent Systems.
255-259

- Thomas Ball, Sriram K. Rajamani:
The SLAM Toolkit.
260-264

Invited Talk
- Xavier Leroy:
Java Bytecode Verification: An Overview.
265-285

Infinite State Systems
Temporal Logics and Verification
Tool Presentations:
Model-Checking and Automata Techniques
- Ilan Beer, Shoham Ben-David, Cindy Eisner, Dana Fisman, Anna Gringauze, Yoav Rodeh:
The Temporal Logic Sugar.
363-367

- Aurore Annichini, Ahmed Bouajjani, Mihaela Sighireanu:
TReX: A Tool for Reachability Analysis of Complex Systems.
368-372

- Peer Johannsen:
BooStER: Speeding Up RTL Property Checking of Digital Designs by Word-Level Abstarction.
373-377

- Vladimir Levin, Hüsnü Yenigün:
SDLcheck: A Model Checking Tool.
377

- Vivek K. Shanbhag, K. Gopinath, Markku Turunen, Ari Ahtiainen, Matti Luukkainen:
EASN: Integrating ASN.1 and Model Checking.
382-386

- Nina Amla, E. Allen Emerson, Robert P. Kurshan, Kedar S. Namjoshi:
Rtdt: A Front-End for Efficient Model Checking of Synchronous Timing Diagrams.
387-390

- Etienne Closse, Michel Poize, Jacques Pulou, Joseph Sifakis, Patrick Venter, Daniel Weil, Sergio Yovine:
TAXYS: A Tool for the Development and Verification of Real-Time Embedded Systems.
391-395

Microprocessor Verification, Cache Coherence
SAT, BDDs, and Applications
- Fady Copty, Limor Fix, Ranan Fraer, Enrico Giunchiglia, Gila Kamhi, Armando Tacchella, Moshe Y. Vardi:
Benefits of Bounded Model Checking at an Industrial Setting.
436-453

- Per Bjesse, Tim Leonard, Abdel Mokkedem:
Finding Bugs in an Alpha Microprocessor Using Satisfiability Solvers.
454-464

- Sumio Morioka, Yasunao Katayama, Toshiyuki Yamane:
Towards Efficient Verification of Arithmetic Algorithms over Galois Fields GF(2m).
465-477

Timed Automata
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