Patrice Quinton, Yves Robert (Eds.):
Algorithms and Parallel VLSI Architectures II, Proceedings of the International Workshop Algorithms and Parallel VLSI Architectures II, Château de Bonas, Gers, France, June 3-6, 1991.
Elsevier 1992, ISBN 0-444-89153-6 
Parallel Algorithms
- John G. McWhirter, Ian K. Proudler:
Orthogonal lattice algorithms for adaptive filtering and beamforming.
11-24
- Miguel Valero-García, Juan J. Navarro, José J. M. Liabería, Mateo Valero, Tomás Lang:
Mapping QR decomposition of a banded matrix on a ID systolic array with data contraflow and pipelined functional units.
25-38
- Marc Moonen:
Algorithms and architectures for recursive total least squares estimation.
39-46
- Rami G. Melhem, John C. Ramirez:
Meshes with flexible redundancy.
47-58
- Selim G. Akl, John M. Calvert, Ivan Stojmenovic:
Systolic generation of derangements.
59-70
- Rumen Andonov, Frédéric Gruau:
A 2D toroidal systolic array for the knapsack problem.
71-78
- Joost-Pieter Katoen, Berry Schoenmakers:
A Parallel program for the recognition of P-Invariant segments.
79-84
- Gur Saran Adhar, Shietung Peng:
Parallel algorithms for finding connected, independent and total domination in interval graphs.
85-90
- Frank K. H. A. Dehne, Andrew Rau-Chaplin:
Parallel algorithms for color image quantization on hypercubes and meshes.
91-96
- Stéphane Ubéda:
A parallel thinning algorithm using the bounding boxes technique.
97-102
- Alle-Jan van der Veen, Patrick Dewilde:
Time-varying system theory for computational networks.
103-130
Synthesis Methodologies
- Weijia Shang, Matthew T. O'Keefe, José A. B. Fortes:
Generalized cycle shrinking.
131-144
- Dimitrios Soudris, Michael K. Birbas, Constantinos E. Goutis:
Direct mapping of nested loops on piecewise regular processor arrays.
145-150
- Vincent Van Dongen:
From systolic to periodic array design.
151-162
- Tanguy Risset:
Linear systolic arrays for matrix multiplication: comparisons of existing synthesis methods and new results.
163-174
- Ravi Varadarajan, Bhavani Ravichandran:
Refinement based algorithm mapping techniques for linear systolic arrays.
175-180
- Jingling Xue, Christian Lengauer:
Specifying control signals for one-dimensional systolic arrays by uniform recurrence equations.
181-186
- Sanjay V. Rajopadhye:
An improved systolic algorithm for the algebraic path problem.
187-198
- Philippe Clauss, Catherine Mongenet, Guy-René Perrin:
Synthesis of size-optimal toroidal arrays for the algebraic path problem.
199-204
- Mokhtar Aboelaze, De-Lei Lee, Benjamin W. Wah:
A programmable VLSI array with constant I/O pins.
205-210
- Francky Catthoor, M. Van Swaalj, Jan Rosseel, Hugo De Man:
Array design methodologies for real-time signal processing in the CATHEDRAL-IV synthesis environment.
211-222
- M. Van Swaalj, Francky Catthoor, Hugo De Man:
Signal analysis and signal transformations for ASIC regular array architecture synthesis.
223-232
VLSI Architectures
- Patrice Frison, Dominique Lavenier:
Experience in the design of paralle processor arrays.
233-242
- John V. McCanny:
On the use of most significant digit first arithmetic in the design of high performance DSP chips.
243-260
- Jean-Michel Muller:
On-line computing: a survey and some new results.
261-272
- Jean Duprat, Mario Fiallos Aguilar, Jean-Michel Muller, Hong-Jin Yeh:
Delays of on-line floating point operators in borrow-save representation.
273-278
- Fawad Rauf, Hassan M. Ahmed:
Nonlinear adaptive filtering algorithms for parallel and systolic implementation.
279-284
- D. K. Arvind:
Distributed simulation of parallel VLSI architectures.
285-298
- Guy Durrieu, Kamel Kessaci, Michel Lemaître:
Transe: an experimental design tool.
299-304
- Frédéric Dufaux, Murat Kunt:
Matrix Multiplication on an associative string processor: application to image compression by Gabor expansion.
305-310
- Henri-Pierre Charles:
Loop unrolling for processors with instruction cache.
311-316
- K. Bouazza, Joël Champeau, P. Ng, Bernard Pottier, Stéphane Rubini:
Implementing cellular automata on the ArMen machine.
317-324
Design Tools
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