CDES 2005:
Las Vegas, Nevada, USA
Laurence Tianruo Yang, Hamid R. Arabnia, Yiming Li, Salam N. Salloum, José G. Delgado-Frias (Eds.):
Proceedings of the 2005 International Conference on Computer Design, CDES 2005, Las Vegas, Nevada, USA, June 27-30, 2005.
CSREA Press 2005, ISBN 1-932415-54-8 
Failure Prevention in Computer Systems
Circuit & Functional Design
- Waleed Al-Assadi, Pavankumar Chandrasekhar, Bonita Bhaskaran:
Fault Modeling and Testability of CMOS Domino Circuits.
21-27
- Daniel R. Blum, Mitchell J. Myjak, José G. Delgado-Frias:
Enhanced Fault-Tolerant Data Latches for Deep Submicron CMOS.
28-34
- Bonita Bhaskaran, Venkat Satagopan, Scott C. Smith:
High-Speed Energy Estimation for Delay-Insensitive Circuits.
35-41
- Derek Nowrouzezahrai, Brian Decker, William Bishop:
High-Performance Double-Precision Cosine Generation.
42-48
- Eugin Hyun, Kyo-Yong Han, Kwang-Su Seong:
Design of PCI 2.2 Target Controller to Support Prefetch Request.
49-58
Network, Communication, & Image Processing
- Koert Vlaeminck, Tim Stevens, Wim Van de Meerssche, Filip De Turck, Bart Dhoedt, Piet Demeester:
Implementation of Network Systems Using Network Processor Technology: Performance Evaluation.
59-63
- Lubomir Ivanov:
Modeling and Verification of a Distributed Transmission Protocol.
64-70
- Eugin Hyun, Kwang-Su Seong:
Design and Verification of I/O Controller for Future Communication System.
71-77
- Bonita Bhaskaran, Venkat Satagopan, Waleed Al-Assadi, Scott C. Smith:
Implementation of Design For Test for Asynchronous NCL Designs.
78-84
- Himanshu Thapliyal, M. B. Srinivas, Rameshwar Rao, Hamid R. Arabnia:
Verilog Coding Style for Efficient Synthesis In FPGA.
85-90
VLSI & SoC:
Technology & Applications
Modeling, Simulation, & Verification
Computer System:
Architecture, Design Methodology, & Implementation
Algorithm, Scheduling, & Performance Technologies
- Daniel Pittman, Dennis Edwards:
Space and Time Efficient Lottery Scheduling.
185-190
- Suryanarayana Tatapudi, José G. Delgado-Frias:
A Pipelined Multiplier Using A Hybrid Wave-Pipelining Scheme.
191-197
- Chung-Chin Luo, Yuan-Shin Hwang, Gene Eu Jan:
Minimal Steiner Trees in X Architecture with Obstacles.
198-203
- Wei-Hao Chiao, Tsung-Hsi Weng, Jean Jyh-Jiun Shann, Chung-Ping Chung, Jimmy Lu:
Low-Power Data Address Bus Encoding Method.
204-210
- Yau-Chong Hu, Wei-Hau Chiao, Jean Jyh-Jiun Shann, Chung-Ping Chung, Wen-Feng Chen:
Low-Power Branch Prediction.
211-217
- Jiann S. Yuan, Jia Di:
Dynamic Active-bit Detection and Operands Exchange for Designing Energy-aware Asynchronous Multipliers.
218-223
- Viktor Bunimov, Manfred Schimmler:
Completely Redundant Modular Exponentiation by Operand Changing.
224-232
Late Papers
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