CDES 2009:
Las Vegas,
Nevada,
USA
Hamid R. Arabnia, Ashu M. G. Solo (Eds.):
Proceedings of the 2009 International Conference on Computer Design, CDES 2009, July 13-16, 2009, Las Vegas Nevada, USA.
CSREA Press 2009, ISBN 1-60132-096-5 
Algorithms,
Logic,
Circuit/Hardware Design,
and Tools
- Ravi Sankar Parameswaran Nair, Scott C. Smith, Jia Di:
Delay-Insensitive Ternary Logic.
3-0
- Richard F. Hobson:
A 5T Sram Cell with 4 Power Terminals for Read/Write/Standby Assist.
10-16
- Indira Dugganapally, Waleed Al-Assadi:
Null Conventional Logic (NCL) Implementation of a Bit-Wise Pipeline Dual-Rail (NCL) 2 (to the power of) S Complement Multiplier.
17-23
- K. S. Vasundara Patel, K. S. Gurumurthy:
Moving From Binary Towards Multi-valued logic.
24-30
- Jong Wook Kwak, Ju-Hwan Kim:
Performance Evaluation Model of Branch Input Vectors using Neural Network.
31-37
- Yong-Sung Jeon, Jong-Wook Han:
Compact Design of a Combined MixColumn/InvMixColumn Transformation Module for AES.
38-41
- Hussain Al-Asaad:
Detection and Isolation of Faulty Processors in Multiprocessor Systems via TMR-Based Time Redundant Task Scheduling.
42-47
- Chung-Han Chen, Saritha Akavaram, Hira N. Narang, Fan Wu:
Yield and Reliability Enhancement for VLSI Design.
48-51
- Rohit Sharma, Nitin Chanderwal, Vivek Kumar Sehgal, Amit Kumar, Preity Gupta, Ashish Nandan Lal:
DELSIC: A Delay Simulator for Interconnect Circuits.
52-56
- Sung-Bin Kim, Se-Jin Ko, Ki-Young Kim, Seok-Yoon Kim:
Reducing the Far-end Crosstalk Using Advanced Guard Trace in PCB Transmission Lines.
57-59
- Ki-Young Kim, Sung-Bin Kim, Se-Jin Ko, Seok-Yoon Kim:
Analytic Models for Peak Current Computation in General Interconnect Circuits.
60-62
Power and Energy
- Nagm Mohamed, Nazeih Botros, Mohamad Alweh:
EPIC: An Energy Exploitative Architecture.
65-69
- Calvin Chiem, Hussain Al-Asaad:
Low Power Methodologies and Challenges for PWM DC-DC Converters.
70-75
- Yashpal Singh, Vikram Singh Yadav, Tarun Kumar:
PES: Power Efficient Scatternet.
76-79
- Yil Suk Yang, Jongdae Kim, Tae Moon Roh, Moon Gyu Jang, Woo Hyun Kwon:
Energy-Aware 32bit Parallel Processing Unit with Multi Operation Modes and 2 Step Data Gating Technique for Multimedia Processor.
80-84
- David Crites, Eric Jordan, Weidong Liao:
A Survey on Power-Aware Computer System Design.
85-89
Embedded Systems + SoC + High-Performance Systems and Design Issues
Novel Applications + Tools/OS
Performance Evaluation + Simulation,
Modeling,
and Testing
Memory,
Cache,
Storage,
Files,
Networking + Device Drivers
- Jack Horner:
Some Power-Law Scaling LImits to Computer Memory Architectures.
159-163
- Jia-Jhe Li, Yuan-Shin Hwang:
Indirect-Mapped Caches: Approximating Set-Associativity with Direct-Mapped Caches.
164-170
- Yoshiyasu Ogasawara, Pulung Waskito, Shinobu Miwa, Hironori Nakajo:
Dynamic Switching Techniques of Accessing L1/L2 Cache on an SMT Processor.
171-177
- Shen-Ming Chung, Shun-Chieh Lin, Chun-Yi Li, Hsiao-Hui Lee, Chi-Chun Chen:
Implementation and Analysis of an Efficient TCP/IP Offload Engine.
178-183
- Antonio Martí Campoy, Francisco Rodríguez-Ballester, Rafael Ors, Juan José Serrano:
Saving Cache Memory Using a Locking Cache in Real-time Systems.
184-189
Late Papers
- Mohamed Ayari, Taoufik Aguili, Helmi Temimi, Henri Baudrand:
EM-Modeling of Excitation Source in Transverse Wave Approach (TWA) for RF Integrated Circuits Applications.
193-199
- Mushtaq Ahmad:
The Computing Technology And John Von Neumann's Computer Architecture Giving Way To Optical Computing.
200-206
- Brett Davis:
CLIW - Clue - Compressed Long Instruction Words.
207-210
- Jorge Ortiz:
A Reconfigurable Superscalar Processor Architecture for FPGA-based Designs.
211-217
Copyright © Tue Nov 24 16:37:59 2009
by Michael Ley (ley@uni-trier.de)
