4. Conference On Computing Frontiers 2007: Ischia, Italy

• Pratap Pattnaik:
  Recent technological trends and their impact on system design. 1-2
  

Memory hierarchy

• Thomas R. Puzak, Allan Hartstein, Philip G. Emma, Viji Srinivasan, Jim Mitchell:
  An analysis of the effects of miss clustering on the cost of a cache miss. 3-12
  
• Ronald G. Dreslinski, Ali G. Saidi, Trevor N. Mudge, Steven K. Reinhardt:
  Analysis of hardware prefetching across virtual page boundaries. 13-22
  
• Albert Meixner, Daniel J. Sorin:
  Unified microprocessor core storage. 23-34
  
• Weidong Shi, Hsien-Hsin S. Lee:
  Accelerating memory decryption and authentication with frequent value prediction. 35-46
  

Mapping applications on parallel platforms

• Jarek Nieplocha, Andrès Márquez, John Feo, Daniel G. Chavarría-Miranda, George Chin Jr., Chad Scherrer, Nathaniel Beagley:
  Evaluating the potential of multithreaded platforms for irregular scientific computations. 47-58
  
• Oystein Thorsen, Brian E. Smith, Carlos P. Sosa, Karl Jiang, Heshan Lin, Amanda E. Peters, Wu-chun Feng:
  Parallel genomic sequence-search on a massively parallel system. 59-68
  
• Kalyan S. Perumalla:
  Scaling time warp-based discrete event execution to 104 processors on a Blue Gene supercomputer. 69-76
  

Quantum computing

• Sarah E. Murphy, Erik DeBenedictis, Peter M. Kogge:
  General floorplan for reversible quantum-dot cellular automata. 77-82
  
• Mark Whitney, Nemanja Isailovic, Yatish Patel, John Kubiatowicz:
  Automated generation of layout and control for quantum circuits. 83-94
  
• Gianfranco Bilardi:
  Models for parallel and hierarchical computation. 95-96
  

Power/energy-efficient micro-architectural techniques

• Hans Vandierendonck, Philippe Manet, Thibault Delavallee, Igor Loiselle, Jean-Didier Legat:
  By-passing the out-of-order execution pipeline to increase energy-efficiency. 97-104
  
• Kaveh Aasaraai, Amirali Baniasadi, Ehsan Atoofian:
  Computational and storage power optimizations for the O-GEHL branch predictor. 105-112
  
• Juan M. Cebrian, Juan L. Aragón, José M. García, Stefanos Kaxiras:
  Adaptive VP decay: making value predictors leakage-efficient designs for high performance processors. 113-122
  
• Hiroshi Sasaki, Yoshimichi Ikeda, Masaaki Kondo, Hiroshi Nakamura:
  An intra-task dvfs technique based on statistical analysis of hardware events. 123-130
  

Software for high-performance systems

• Christophe Dubach, John Cavazos, Björn Franke, Grigori Fursin, Michael F. P. O'Boyle, Olivier Temam:
  Fast compiler optimisation evaluation using code-feature based performance prediction. 131-142
  
• Tipp Moseley, Daniel A. Connors, Dirk Grunwald, Ramesh Peri:
  Identifying potential parallelism via loop-centric profiling. 143-152
  
• Geoffroy Vallée, Thomas Naughton, Stephen L. Scott:
  System management software for virtual environments. 153-160
  

Reconfigurable architectures

• Grigoris Dimitroulakos, Michalis D. Galanis, Nikos Kostaras, Costas E. Goutis:
  A unified evaluation framework for coarse grained reconfigurable array architectures. 161-172
  
• Daniel G. Chavarría-Miranda, Andrès Márquez:
  Assessing the potential of hybrid hpc systems for scientific applications: a case study. 173-182
  
• Shoaib Kamil, Ali Pinar, Daniel Gunter, Michael Lijewski, Leonid Oliker, John Shalf:
  Reconfigurable hybrid interconnection for static and dynamic scientific applications. 183-194
  
• Philippe Jorrand:
  The quantum challenge to computer science. 195-196
  

Novel parallel hardware platforms

• Shinichi Yamagiwa, Leonel Sousa:
  Design and implementation of a stream-based distributedcomputing platform using graphics processing units. 197-204
  
• Shinichi Yamagiwa, Leonel Sousa, Diogo Antão:
  Data buffering optimization methods toward a uniform programming interface for gpu-based applications. 205-212
  
• Satoshi Amamiya, Masaaki Izumi, Takanori Matsuzaki, Ryuzo Hasegawa, Makoto Amamiya:
  Fuce: the continuation-based multithreading processor. 213-224
  
• Shigeru Kusakabe, Mitsuhiro Aono, Masaaki Izumi, Satoshi Amamiya, Yoshinari Nomura, Hideo Taniguchi, Makoto Amamiya:
  Scalability of continuation-based fine-grained multithreading in handling multiple I/O requests on FUCE. 225-236
  

Memory management in parallel systems

• Matthew E. Tolentino, Joseph Turner, Kirk W. Cameron:
  Memory-miser: a performance-constrained runtime system for power-scalable clusters. 237-246
  
• Michela Becchi, Mark A. Franklin, Patrick Crowley:
  Performance/area efficiency in chip multiprocessors with micro-caches. 247-258
  
• Ehsan Atoofian, Amirali Baniasadi, Kaveh Aasaraai:
  Speculative supplier identification for reducing power of interconnects in snoopy cache coherence protocols. 259-266
  

SIMD architectures

• Tirath Ramdas, Gregory K. Egan, David Abramson, Kim Baldridge:
  Converting massive TLP to DLP: a special-purpose processor for molecular orbital computations. 267-276
  
• Philippe Marquet, Simon Duquennoy, Sébastien Le Beux, Samy Meftali, Jean-Luc Dekeyser:
  Massively parallel processing on a chip. 277-286