13. CHARME 2005:
: Is Formal Verification Bound to Remain a Junior Partner of Simulation?
Functional Approaches to Design Description
Algorithms and Techniques for Speeding (DD-Based) Verification 1
Real Time and LTL Model Checking
Algorithms and Techniques for Speeding Verification 2
, Hari Mony
: Maximal Input Reduction of Sequential Netlists via Synergistic Reparameterization and Localization Strategies.
Evaluation of SAT-Based Tools
Verification of Memory Hierarchy Mechanisms
: Behavior-RTL Equivalence Checking Based on Data Transfer Analysis with Virtual Controllers and Datapaths.
: A Case Study: Formal Verification of Processor Critical Properties.