CHDL 1993: Ottawa, Ontario, Canada
David Agnew, Luc J. M. Claesen, Raul Camposano (Eds.): Computer Hardware Description Languages and their Applications, Proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications - CHDL '93, sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC, Ottawa, Ontario, Canada, 26-28 April, 1993. North-Holland 1993 IFIP Transactions ISBN 0-444-81641-0- Mario Barbacci: Real Time Distributed Systems. 3-12
Session: BDD-based Design and Analysis Techniques
- Edmund M. Clarke, Orna Grumberg, Hiromi Hiraishi, Somesh Jha, David E. Long, Kenneth L. McMillan, Linda A. Ness: Verification of the Futurebus+ Cache Coherence Protocol. 15-30
- Paolo Camurati, Fulvio Corno, Paolo Prinetto: Exploiting Symbolic Traversal Techniques for Efficient Process Algebra Manipulation. 31-44
Session: HDL-based Design Methods
- Klaus Buchenrieder, Alexander Sedlmeier, Christian Veith: HW/SW Co-Design with PRAMs Using CoDES. 65-78
- Flávio Rech Wagner: Prevail-DM: A Framework-Based Environment for Formal Hardware Verification. 79-96
Session: Synthesis and Verification
- Michel Allemand: A Rewriting Based Method for the Formal Verification of Microprocessors. 115-122
- J. W. Gambles, Phillip J. Windley: Reasoning about the VHDL Standard Logic Package Signal Data Type. 123-130
- Xing-Jian Xu, Mitsuru Ishizuka: An Efficient Data-Path Synthesis Based on Algorithmic Description under the Constraints of Time and Area. 131-138
- Bhaskar Bose, Steven D. Johnson, Shyamsundar Pullela: Integrating Boolean Verification with Formal Derivation. 139-146
- Francisco Corella: Automated High-level Verification Against Clocked Algorithmic Specifications. 147-154
- Stefan Krischer: The Backward Walk Approach in FSM Verification. 155-162
- Edmund M. Clarke: Automatic Verification of Sequential Circuit Designs. 165
Session: Protocol Specification
- Kamlesh Rath, Steven D. Johnson: Toward a Basis for Protocol Specification and Process Decomposition. 169-186
- Wolfgang Glunz, Thomas Kruse, Torsten Rössel, Dieter Monjau: Integrating SDL and VHDL for System-Level Hardware Design. 187-204
Session: Formal Reasoning about Regular Structures
- Laurence Pierre: VHDL Description and Formal Verification of Systolic Multipliers. 225-242
Session: High Level Synthesis
- Roger P. Ang, Nikil D. Dutt: A Representation for the Binding of RT-Component Functionality to HDL Behavior. 263-280
Session: Design Capture (short papers)
- John W. O'Leary, Mark H. Linderman, Miriam Leeser, Mark Aagaard: HML: A Hardware Description Language Based on Standard ML. 327-334
- Bran Selic: An Efficient Object-Oriented Variation of the Statecharts Formalism for Distributed Real-Time Systems. 335-344
- Ahmed Amine Jerraya, Kevin O'Brien, Tarek Ben Ismail: Linking System Design Tools and Hardware Design Tools. 345-351
- Balraj Singh, John R. Wicks, Philip Wright, James R. Armstrong: The Modeler's Assistant: A CAD Tool for Behavioral Model Development. 361-368
- Shailesh Sutarwala, Pierre G. Paulin, Yatish Kumar: Insulin: An Instruction Set Simulation Environment. 369-376
- Gregor von Bochmann: Specification Languages for Communication Protocols. 379-396
Session: Timing Specifications in HDLs
- Karim Khordoc, Mario Dufresne, Eduard Cerny, P. A. Babkine, Allan Silburt: Integrating Behavior and Timing in Executable Specifications. 399-416
- Tam Anh Chu, Huy T. Cao, Clement K. C. Leung: ESP: An Executable Specification Language for Mixed Timing Control Circuits. 417-434
Session: Textual and Graphical HDLs
- Tamio Hoshino: UDL/I version Two: A New Horizon of HDL Standards. 437-452
- Walling R. Cyre: Textual/Graphical Design Concept-Level Synthesis. 485-502
Session: VHDL
- Wolfgang Ecker, Sabine März: System-Level Specification and Design Using VHDL: A Case Study. 505-522
- Karen C. Davis: A Denotational Definition of the VHDL Simulation Kernel. 523-535
- Michael Ryba, Wolfram Seibold, Utz G. Baitinger, Ulrich Thelen: Parameterized VHDL Entities for the Simulation of Hybrid Circuits. 551-567
- Zainalabedin Navabi, Amirhooshang Hashemi, Massoud Eghtesad, Mankuan Michael Vai: Modeling Timing Behavior of Logic Circuits Using Piecewise Linear Models. 569-586
- Dominique Rodriguez: Analog-VHDL: As an Application, a Real Example. 587-604
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