7. CHES 2005: Edinburgh, UK

Side Channels I

• William Dupuy, Sébastien Kunz-Jacques:
  Resistance of Randomized Projective Coordinates Against Power Analysis. 1-14
  
• Dakshi Agrawal, Josyula R. Rao, Pankaj Rohatgi, Kai Schramm:
  Templates as Master Keys. 15-29
  
• Werner Schindler, Kerstin Lemke, Christof Paar:
  A Stochastic Model for Differential Side Channel Cryptanalysis. 30-46
  

Arithmetic for Cryptanalysis

• Jean-Sébastien Coron, David Lefranc, Guillaume Poupard:
  A New Baby-Step Giant-Step Algorithm and Some Applications to Cryptanalysis. 47-60
  
• P. J. Green, Richard Noad, Nigel P. Smart:
  Further Hidden Markov Model Cryptanalysis. 61-74
  

Low Resources

• Johann Großschädl, Roberto Maria Avanzi, Erkay Savas, Stefan Tillich:
  Energy-Efficient Software Implementation of Long Integer Modular Arithmetic. 75-90
  
• Katsuyuki Okeya, Tsuyoshi Takagi, Camille Vuillaume:
  Short Memory Scalar Multiplication on Koblitz Curves. 91-105
  
• Lejla Batina, David Hwang, Alireza Hodjat, Bart Preneel, Ingrid Verbauwhede:
  Hardware/Software Co-design for Hyperelliptic Curve Cryptography (HECC) on the 8051µP. 106-118
  

Special Purpose Hardware

• Jens Franke, Thorsten Kleinjung, Christof Paar, Jan Pelzl, Christine Priplata, Colin Stahlke:
  SHARK: A Realizable Special Hardware Sieving Device for Factoring 1024-Bit Integers. 119-130
  
• Willi Geiselmann, Adi Shamir, Rainer Steinwandt, Eran Tromer:
  Scalable Hardware for Sparse Systems of Linear Equations, with Applications to Integer Factorization. 131-146
  
• Marco Bucci, Raimondo Luzzi:
  Design of Testable Random Bit Generators. 147-156
  

Hardware Attacks and Countermeasures I

• Stefan Mangard, Norbert Pramstaller, Elisabeth Oswald:
  Successfully Attacking Masked AES Hardware Implementations. 157-171
  
• Thomas Popp, Stefan Mangard:
  Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints. 172-186
  
• Wieland Fischer, Berndt M. Gammel:
  Masking at Gate Level in the Presence of Glitches. 187-200
  

Arithmetic for Cryptography

• Marcelo E. Kaihara, Naofumi Takagi:
  Bipartite Modular Multiplication. 201-210
  
• Laszlo Hars:
  Fast Truncated Multiplication for Cryptographic Applications. 211-225
  
• Martin Seysen:
  Using an RSA Accelerator for Modular Inversion. 226-236
  
• Berk Sunar, David Cyganski:
  Comparison of Bit and Word Level Algorithms for Evaluating Unstructured Functions over Finite Rings. 237-249
  

Side Channel II (EM)

• Catherine H. Gebotys, Simon Ho, C. C. Tiu:
  EM Analysis of Rijndael and ECC on a Wireless Java-Based PDA. 250-264
  
• Markus G. Kuhn:
  Security Limits for Compromising Emanations. 265-279
  
• Huiyun Li, A. Theodore Markettos, Simon W. Moore:
  Security Evaluation Against Electromagnetic Analysis at Design Time. 280-292
  

Side Channel III

• Marc Joye, Pascal Paillier, Berry Schoenmakers:
  On Second-Order Differential Power Analysis. 293-308
  
• Eric Peeters, François-Xavier Standaert, Nicolas Donckers, Jean-Jacques Quisquater:
  Improved Higher-Order Side-Channel Attacks with FPGA Experiments. 309-323
  

Trusted Computing

• Ulrich Kühn, Klaus Kursawe, Stefan Lucks, Ahmad-Reza Sadeghi, Christian Stüble:
  Secure Data Management in Trusted Computing. 324-338
  

Hardware Attacks and Countermeasures II

• Sergei P. Skorobogatov:
  Data Remanence in Flash Memory Devices. 339-353
  
• Kris Tiri, David D. Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede:
  Prototype IC with WDDL and Differential Routing - DPA Resistance Assessment. 354-365
  

Hardware Attacks and Countermeasures III

• Daisuke Suzuki, Minoru Saeki, Tetsuya Ichikawa:
  DPA Leakage Models for CMOS Logic Circuits. 366-382
  
• Sylvain Guilley, Philippe Hoogvorst, Yves Mathieu, Renaud Pacalet:
  The "Backend Duplication" Method. 383-397
  

Efficient Hardware I

• Philipp Grabher, Dan Page:
  Hardware Acceleration of the Tate Pairing in Characteristic Three. 398-411
  
• Tim Kerins, William P. Marnane, Emanuel M. Popovici, Paulo S. L. M. Barreto:
  Efficient Hardware for the Tate Pairing Calculation in Characteristic Three. 412-426
  

Efficient Hardware II

• Tim Good, Mohammed Benaissa:
  AES on FPGA from the Fastest to the Smallest. 427-440
  
• David Canright:
  A Very Compact S-Box for AES. 441-455
  

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