Alex Orailoglu, Pai H. Chou, Petru Eles, Axel Jantsch (Eds.): Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2004, Stockholm, Sweden, September 8-10, 2004. ACM 2004 ISBN 1-58113-937-3- Andrea Cuomo: Future challenges in embedded systems. 1
Special session on organic computing
- Christian Müller-Schloer: Organic computing: on the feasibility of controlled emergence. 2-5
New design techniques for application specific processors
- Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran: Dual-pipeline heterogeneous ASIP design. 12-17
- Scott J. Weber, Matthew W. Moskewicz, Matthias Gries, Christian Sauer, Kurt Keutzer: Fast cycle-accurate simulation and instruction set generation for constraint-based descriptions of programmable architectures. 18-23
Advances in software and hardware synthesis techniques for DSP applications
- Hyunuk Jung, Soonhoi Ha: Hardware synthesis from coarse-grained dataflow specification for fast HW/SW cosynthesis. 24-29
- Fredy Rivera, Marcos Sanchez-Elez, Milagros Fernández, Román Hermida, Nader Bagherzadeh: Efficient mapping of hierarchical trees on coarse-grain reconfigurable architectures. 30-35
- Gwenolé Corre, Eric Senn, Pierre Bomel, Nathalie Julien, Eric Martin: Memory accesses management during high level synthesis. 42-47
Multiprocessor SoC: design strategies and programming models
- Pierre G. Paulin, Chuck Pilkington, Michel Langevin, Essaid Bensoudane, Gabriela Nicolescu: Parallel programming models for a multi-processor SoC platform applied to high-speed traffic management. 48-53
- JoAnn M. Paul, Donald E. Thomas, Alex Bobrek: Benchmark-based design strategies for single chip heterogeneous multiprocessors. 54-59
- Basant Kumar Dwivedi, Anshul Kumar, M. Balakrishnan: Automatic synthesis of system on chip multiprocessor architectures for process networks. 60-65
- Xinping Zhu, Wei Qin, Sharad Malik: Modeling operation and microarchitecture concurrency for communication architectures with application to retargetable simulation. 66-71
Panel Session
- Peter Marwedel, Catherine H. Gebotys: Secure and safety-critical vs. insecure, non safety-critical embedded systems: do they require completely different design approaches? 72
- Sven Mattisson: Keynote: cellular handset technology system requirements and integration trends. 74
New modeling approaches and their application
- Adam Donlin: Transaction level modeling: flows and use models. 75-80
- Luigi Pomante: Exploiting polymorphism in HW design: a case study in the ATM domain. 81-85
- Manish Vachharajani, Neil Vachharajani, Sharad Malik, David I. August: Facilitating reuse in hardware models with enhanced type inference. 86-91
- Qiang Zhu, Ryosuke Oishi, Takashi Hasegawa, Tsuneo Nakata: System-on-chip validation using UML and CWL. 92-97
- Mahmut T. Kandemir, Ismail Kadayif, Guilin Chen: Compiler-directed code restructuring for reducing data TLB energy. 98-103
Energy-aware compiling and scheduling
- Manish Verma, Lars Wehmeyer, Peter Marwedel: Dynamic overlay of scratchpad memory for energy minimization. 104-109
- Haisang Wu, Binoy Ravindran, E. Douglas Jensen, Peng Li: CPU scheduling for statistically-assured real-time performance and improved energy efficiency. 110-115
System-level design space exploration for hardware-software partitioning and platform instantiation
- Sudarshan Banerjee, Nikil D. Dutt: Efficient search space exploration for HW-SW partitioning. 122-127
- Alexander Maxiaguine, Yongxin Zhu, Samarjit Chakraborty, Weng-Fai Wong: Tuning SoC platforms for multimedia processing: identifying limits and tradeoffs. 128-133
Estimation and design techniques for energy-efficient memory systems
- Chin-Hsien Wu, Tei-Wei Kuo, Chia-Lin Yang: Energy-efficient flash-memory storage systems with an interrupt-emulation mechanism. 134-139
- Rajeev Krishna, Scott A. Mahlke, Todd M. Austin: Memory system design space exploration for low-power, real-time speech recognition. 140-145
- Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt, Magdy S. Abadir: Analytical models for leakage power estimation of memory array structures. 146-151
Advances in hardware/software co-simulation techniques
- Luca Formaggio, Franco Fummi, Graziano Pravadelli: A timing-accurate HW/SW co-simulation of an ISS with SystemC. 152-157
- Shinya Honda, Takayuki Wakabayashi, Hiroyuki Tomiyama, Hiroaki Takada: RTOS-centric hardware/software cosimulator for embedded system design. 158-163
- Zhengting He, Aloysius K. Mok: Fast co-simulation of transformative systems with OS support on SMP computer. 164-169
- Dongkun Shin, Jihong Kim: Power-aware communication optimization for networks-on-chips with voltage scalable links. 170-175
- Erland Nilsson, Johnny Öberg: Reducing power and latency in 2-D mesh NoCs using globally pseudochronous locally synchronous clocking. 176-181
- Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi: Multi-objective mapping for mesh-based NoC architectures. 182-187
- Paul Marchal, José Ignacio Gómez, Francky Catthoor: Optimizing the memory bandwidth with loop fusion. 188-193
- Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, Alexandru Nicolau: Operation tables for scheduling in the presence of incomplete bypassing. 194-199
- Jaehwan Lee, Vincent John Mooney III: A novel deadlock avoidance algorithm and its hardware implementation. 200-205
- Pieter van der Wolf, Erwin A. de Kock, Tomas Henriksson, Wido Kruijtzer, Gerben Essink: Design and programming of embedded multiprocessors: an interface-centric approach. 206-217
- Radu Muresan, Catherine H. Gebotys: Current flattening in software and hardware for security applications. 218-223
- Catherine H. Gebotys: Low energy security optimization in embedded cryptographic systems. 224-229
- Guilin Chen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Mary Jane Irwin: Analyzing heap error behavior in embedded JVM environments. 230-235
- Kanishka Lahiri, Anand Raghunathan: Power analysis of system-level on-chip communication architectures. 236-241
- Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane: Fast exploration of bus-based on-chip communication architectures. 242-247
- Sungchan Kim, Chaeseok Im, Soonhoi Ha: Efficient exploration of on-chip bus architectures and memory allocation. 248-253
- Peter Marwedel, Daniel Gajski, Erwin A. de Kock, Hugo De Man, Mariagiovanna Sami, Ingemar Söderquist: Embedded systems education: how to teach the required skills? 254-255
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last updated on 2013-06-18T211851 by the dblp team